Nadav Rotem 0877fdf30b Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant generate a shuffle node from two vectors of different types. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150383 91177308-0d34-0410-b5e6-96231b3b80d8		2012-02-13 12:42:26 +00:00
..
ARM	RegAlloc superpass: includes phi elimination, coalescing, and scheduling.	2012-02-10 04:10:36 +00:00
CBackend
CellSPU	This patch addresses the problem of poor code generation for the zext	2012-02-12 15:05:31 +00:00
CPP	Testcase for commit 149833 (use of an uninitialized variable noticed	2012-02-05 19:27:57 +00:00
Generic	Move test/CodeGen/Generic/2012-02-01-CoalescerBug.ll to CodeGen/ARM, for now. It requires TARGETS=arm.	2012-02-02 11:44:58 +00:00
Hexagon	VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).	2012-02-01 22:13:57 +00:00
MBlaze
Mips	Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is	2012-02-03 04:33:00 +00:00
MSP430
PowerPC	AggressiveAntiDepBreaker needs to skip debug values because a debug value does not have a corresponding SUnit	2012-01-16 22:53:41 +00:00
PTX
SPARC
Thumb
Thumb2	After r147827 and r147902, it's now possible for unallocatable registers to be	2012-01-14 01:53:46 +00:00
X86	Fix a bug in DAGCombine for the optimization of BUILD_VECTOR. We cant generate a shuffle node from two vectors of different types.	2012-02-13 12:42:26 +00:00
XCore