llvm-6502/test/MC/Disassembler/X86
2014-12-26 18:20:05 +00:00
..
avx-512.txt AVX-512: Fixed encoding of VPBROADCASTM and added SKX forms of this instruction 2014-10-26 09:52:24 +00:00
fp-stack.txt Add two fp test cases I missed in my previous commit. 2013-12-31 23:15:19 +00:00
hex-immediates.txt llvm-mc: Add option for prefering hex format disassembly. 2014-06-11 20:26:40 +00:00
intel-syntax-32.txt
intel-syntax.txt Fixing Intel format of the vshufpd instruction. 2013-09-27 01:44:23 +00:00
invalid-VEX-vvvv.txt
lit.local.cfg Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00
marked-up.txt
missing-sib.txt Test case for r204305. 2014-03-20 06:45:10 +00:00
moffs.txt llvm-mc: Add option for prefering hex format disassembly. 2014-06-11 20:26:40 +00:00
padlock.txt Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. 2014-02-19 05:34:21 +00:00
prefixes.txt [X86] Add the debug registers DR8-DR15 so we can assemble and disassemble references to them. 2014-12-26 18:20:05 +00:00
simple-tests.txt Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 2014-01-01 15:29:32 +00:00
truncated-input.txt
x86-16.txt [x86] Fix 16-bit disassembly of JCXZ/JECXZ 2014-01-20 12:02:48 +00:00
x86-32.txt Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4. 2014-12-26 06:36:28 +00:00
x86-64.txt Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860. 2014-02-17 10:03:43 +00:00