mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-29 13:29:28 +00:00
With the change the disassembler now supports the XCore ISA in its entirety. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8
707 lines
8.7 KiB
Plaintext
707 lines
8.7 KiB
Plaintext
# RUN: llvm-mc --disassemble %s -triple=xcore-xmos-elf | FileCheck %s
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# 0r instructions
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# CHECK: clre
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0xed 0x07
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# CHECK: get r11, id
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0xee 0x17
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# CHECK: get r11, ed
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0xfe 0x0f
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# CHECK: get r11, et
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0xff 0x0f
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# CHECK: ssync
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0xee 0x07
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# CHECK: waiteu
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0xec 0x07
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# CHECK: dcall
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0xfc 0x07
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# CHECK: dentsp
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0xec 0x17
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# CHECK: drestsp
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0xed 0x17
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# CHECK: dret
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0xfe 0x07
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# CHECK: freet
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0xef 0x07
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# CHECK: get r11, kep
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0xef 0x17
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# CHECK: get r11, ksp
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0xfc 0x17
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# CHECK: kret
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0xfd 0x07
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# CHECK: ldw et, sp[4]
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0xfe 0x17
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# CHECK: ldw sed, sp[3]
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0xfd 0x17
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# CHECK: ldw spc, sp[1]
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0xec 0x0f
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# CHECK: ldw ssr, sp[2]
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0xee 0x0f
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# CHECK: set kep, r11
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0xff 0x07
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# CHECK: stw et, sp[4]
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0xfd 0x0f
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# CHECK: stw sed, sp[3]
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0xfc 0x0f
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# CHECK: stw spc, sp[1]
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0xed 0x0f
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# CHECK: stw ssr, sp[2]
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0xef 0x0f
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# 1r instructions
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# CHECK: msync res[r0]
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0xf0 0x1f
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# CHECK: mjoin res[r1]
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0xf1 0x17
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# CHECK: bau r2
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0xf2 0x27
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# CHECK: set sp, r3
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0xf3 0x2f
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# CHECK: ecallt r4
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0xf4 0x4f
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# CHECK: ecallf r5
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0xe5 0x4f
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# CHECK: bla r6
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0xe6 0x27
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# CHECK: bru r8
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0xe8 0x2f
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# CHECK: syncr res[r7]
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0xf7 0x87
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# CHECK: freer res[r8]
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0xe8 0x17
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# CHECK: setv res[r9], r11
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0xf9 0x47
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# CHECK: setev res[r10], r11
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0xfa 0x3f
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# CHECK: eeu res[r11]
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0xfb 0x07
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# CHECK: set dp, r5
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0xe5 0x37
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# CHECK: set cp, r0
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0xf0 0x37
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# CHECK: dgetreg r11
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0xeb 0x3f
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# CHECK: edu res[r8]
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0xe8 0x07
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# CHECK: kcall r2
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0xe2 0x47
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# CHECK: waitef r10
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0xfa 0x0f
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# CHECK: waitet r7
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0xe7 0x0f
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# CHECK: start t[r4]
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0xe4 0x1f
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# CHECK: clrpt res[r9]
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0xe9 0x87
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# 2r instructions
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# CHECK: not r1, r8
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0x24 0x8f
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# CHECK: neg r7, r6
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0xce 0x97
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# CHECK: andnot r10, r11
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0xab 0x2f
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# CHECK: mkmsk r11, r0
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0x4c 0xa7
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# CHECK: getts r8, res[r1]
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0x41 0x3f
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# CHECK: setpt res[r2], r3
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0xde 0x3e
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# CHECK: outct res[r1], r2
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0xc6 0x4e
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# CHECK: outt res[r5], r4
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0xd1 0x0f
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# CHECK: out res[r9], r10
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0xa9 0xaf
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# CHECK: outshr res[r0], r2
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0xd8 0xae
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# CHECK: inct r7, res[r4]
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0xdc 0x87
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# CHECK: int r8, res[r3]
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0x53 0x8f
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# CHECK: in r10, res[r0]
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0x48 0xb7
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# CHECK: inshr r4, res[r2]
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0x12 0xb7
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# CHECK: chkct res[r6], r0
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0x08 0xcf
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# CHECK: testct r8, res[r3]
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0x53 0xbf
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# CHECK: testwct r2, res[r9]
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0x39 0xc7
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# CHECK: setd res[r3], r4
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0x13 0x17
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# CHECK: getst r7, res[r1]
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0x1d 0x07
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# CHECK: init t[r1]:sp, r2
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0xc9 0x16
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# CHECK: init t[r10]:pc, r1
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0x26 0x07
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# CHECK: init t[r2]:cp, r10
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0x4a 0x1f
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# CHECK: init t[r2]:dp, r3
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0xce 0x0e
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# CHECK: setpsc res[r8], r2
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0x28 0xc7
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# CHECK: zext r3, r8
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0x2c 0x47
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# CHECK: sext r9, r1
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0x45 0x37
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# CHECK: tsetmr r7, r3
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0x1f 0x1f
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# CHECK: eef r1, res[r6]
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0x96 0x2f
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# CHECK: eet r11, res[r0]
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0x5c 0x27
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# rus instructions
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# CHECK: chkct res[r1], 8
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0x34 0xcf
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# CHECK: getr r11, 2
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0x4e 0x87
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# CHECK: mkmsk r4, 24
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0x72 0xa7
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# CHECK: outct res[r3], 0
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0xdc 0x4e
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# CHECK: sext r8, 16
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0xb1 0x37
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# CHECK: zext r2, 32
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0xd8 0x46
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# CHECK: peek r0, res[r5]
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0x81 0xbf
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# CHECK: endin r10, res[r1]
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0x59 0x97
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# l2r instructions
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# CHECK: bitrev r1, r10
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0x26 0xff 0xec 0x07
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# CHECK: byterev r4, r1
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0x11 0xff 0xec 0x07
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# CHECK: clz r11, r10
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0xae 0xff 0xec 0x0f
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# CHECK: get r3, ps[r6]
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0x9e 0xff 0xec 0x17
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# CHECK: setc res[r5], r9
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0x75 0xff 0xec 0x2f
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# CHECK: init t[r2]:lr, r1
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0xc6 0xfe 0xec 0x17
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# CHECK: setclk res[r2], r1
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0xd6 0xfe 0xec 0x0f
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# CHECK: set ps[r9], r10
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0xa9 0xff 0xec 0x1f
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# CHECK: setrdy res[r3], r1
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0xc7 0xfe 0xec 0x2f
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# CHECK: settw res[r7], r2
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0x9b 0xff 0xec 0x27
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# CHECK: getd r8, res[r3]
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0x53 0xff 0xec 0x1f
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# CHECK: getn r10, res[r11]
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0xbb 0xff 0xec 0x37
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# CHECK: testlcl r2, res[r0]
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0xc8 0xfe 0xec 0x27
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# CHECK: setn res[r9], r7
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0x6d 0xff 0xec 0x37
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# 3r instructions
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# CHECK: add r1, r2, r3
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0x1b 0x10
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# CHECK: and r11, r10, r9
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0xb9 0x3e
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# CHECK: eq r6, r1, r2
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0x66 0x30
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# CHECK: ld16s r8, r3[r4]
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0xcc 0x82
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# CHECK: ld8u r9, r1[r10]
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0x16 0x8d
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# CHECK: ldw r9, r4[r5]
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0x91 0x4b
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# CHECK: lss r7, r3, r0
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0x7c 0xc0
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# CHECK: lsu r5, r8, r6
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0x12 0xcc
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# CHECK: or r1, r3, r2
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0x1e 0x40
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# CHECK: shl r8, r2, r4
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0xc8 0x22
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# CHECK: shr r9, r7, r1
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0x5d 0x29
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# CHECK: sub r4, r2, r5
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0x89 0x1a
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# CHECK: set t[r0]:r1, r2
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0x18 0xb8
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# 2rus instructions
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# CHECK: add r10, r2, 5
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0xe9 0x92
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# CHECK: eq r2, r1, 0
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0x24 0xb0
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# CHECK: ldw r5, r6[1]
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0x19 0x09
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# CHECK: shl r6, r5, 24
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0xa6 0xa5
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# CHECK: shr r3, r8, 5
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0xf1 0xab
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# CHECK: stw r3, r2[0]
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0x38 0x00
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# CHECK: sub r2, r4, 11
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0x63 0x9d
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# l3r instructions
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# CHECK: ashr r5, r1, r11
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0xd7 0xfc 0xec 0x17
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# CHECK: crc32 r5, r6, r1
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0x19 0xf9 0xec 0xaf
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# CHECK: divu r9, r1, r3
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0x97 0xf8 0xec 0x4f
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# CHECK: divs r6, r7, r2
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0x2e 0xf9 0xec 0x47
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# CHECK: lda16 r11, r2[r1]
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0xb9 0xf8 0xec 0x2f
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# CHECK: lda16 r9, r3[-r11]
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0x1f 0xfd 0xec 0x37
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# CHECK: ldaw r9, r1[r2]
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0x96 0xf8 0xec 0x1f
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# CHECK: ldaw r8, r7[-r11]
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0xcf 0xfd 0xec 0x27
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# CHECK: mul r0, r4, r2
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0xc2 0xf8 0xec 0x3f
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# CHECK: remu r1, r2, r3
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0x1b 0xf8 0xec 0xcf
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# CHECK: rems r11, r10, r9
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0xb9 0xfe 0xec 0xc7
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# CHECK: st16 r5, r3[r8]
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0xdc 0xfc 0xec 0x87
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# CHECK: st8 r9, r1[r3]
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0x97 0xf8 0xec 0x8f
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# CHECK: stw r7, r10[r1]
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0xf9 0xf9 0xec 0x07
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# CHECK: xor r4, r3, r9
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0xcd 0xfc 0xec 0x0f
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# l2rus instructions
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# CHECK: ashr r5, r1, 3
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0x57 0xf8 0xec 0x97
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# CHECK: ldaw r11, r10[6]
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0x7a 0xfc 0xec 0x9f
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# CHECK: ldaw r8, r2[-9]
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0x09 0xfd 0xec 0xa7
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# CHECK: inpw r6, res[r1], 8
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0xe4 0xfc 0xee 0x97
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# CHECK: outpw res[r3], r0, 2
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0x0e 0xf8 0xed 0x97
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# ru6 / lru6 instructions
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# CHECK: bt r6, -5
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0x85 0x75
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# CHECK: bt r10, -451
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0x07 0xf0 0x83 0x76
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# CHECK: bt r8, 10
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0x0a 0x72
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# CHECK: bt r1, 6451
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0x64 0xf0 0x73 0x70
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# CHECK: bf r5, 8
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0x48 0x79
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# CHECK: bf r6, 65
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0x01 0xf0 0x81 0x79
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# CHECK: bf r1, 53
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0x75 0x78
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# CHECK: bf r10, 101
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0x01 0xf0 0xa5 0x7a
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# CHECK: ldaw r11, dp[63]
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0xff 0x62
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# CHECK: ldaw r1, dp[456]
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0x07 0xf0 0x48 0x60
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# CHECK: ldaw cp, dp[5]
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0x05 0x63
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# CHECK: ldaw sp, dp[9929]
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0x9b 0xf0 0x89 0x63
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# CHECK: ldaw r3, sp[2]
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0xc2 0x64
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# CHECK: ldaw r8, sp[65535]
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0xff 0xf3 0x3f 0x66
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# CHECK: ldaw sp, sp[41]
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0xa9 0x67
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# CHECK: ldaw sp, sp[13121]
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0xcd 0xf0 0x81 0x67
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# CHECK: ldc r3, 30
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0xde 0x68
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# CHECK: ldc r11, 1000
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0x0f 0xf0 0xe8 0x6a
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# CHECK: ldc sp, 0
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0x80 0x6b
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# CHECK: ldc lr, 81
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0x01 0xf0 0xd1 0x6b
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# CHECK: ldw r0, cp[4]
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0x04 0x6c
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# CHECK: ldw r1, cp[32345]
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0xf9 0xf1 0x59 0x6c
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# CHECK: ldw cp, cp[8]
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0x08 0x6f
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# CHECK: ldw sp, cp[10222]
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0x9f 0xf0 0xae 0x6f
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# CHECK: ldw r10, dp[16]
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0x90 0x5a
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# CHECK: ldw r10, dp[76]
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0x01 0xf0 0x8c 0x5a
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# CHECK: ldw lr, dp[8]
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0xc8 0x5b
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# CHECK: ldw dp, dp[33221]
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0x07 0xf2 0x45 0x5b
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# CHECK: ldw r8, sp[51]
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0x33 0x5e
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# CHECK: ldw r8, sp[1225]
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0x13 0xf0 0x09 0x5e
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# CHECK: ldw cp, sp[31]
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0x1f 0x5f
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# CHECK: ldw sp, sp[1000]
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0x0f 0xf0 0xa8 0x5f
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# CHECK: setc res[r5], 36
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0x64 0xe9
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# CHECK: setc res[r2], 40312
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0x75 0xf2 0xb8 0xe8
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# CHECK: stw r8, dp[14]
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0x0e 0x52
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# CHECK: stw r9, dp[654]
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0x0a 0xf0 0x4e 0x52
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# CHECK: stw lr, dp[23]
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0xd7 0x53
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# CHECK: stw sp, dp[44442]
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0xb6 0xf2 0x9a 0x53
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# CHECK: stw r1, sp[32]
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0x60 0x54
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# CHECK: stw r0, sp[8761]
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0x88 0xf0 0x39 0x54
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# CHECK: stw cp, sp[63]
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0x3f 0x57
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# CHECK: stw lr, sp[4391]
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0x44 0xf0 0xe7 0x57
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# u6 / lu6 instructions
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# CHECK: bu -20
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0x14 0x77
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# CHECK: bu -1000
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0x0f 0xf0 0x28 0x77
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# CHECK: bu 24
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0x18 0x73
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# CHECK: bu 2231
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0x22 0xf0 0x37 0x73
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# CHECK: extsp 9
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0x89 0x77
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# CHECK: extsp 5721
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0x59 0xf0 0x99 0x77
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# CHECK: clrsr 60
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0x3c 0x7b
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# CHECK: clrsr 64391
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0xee 0xf3 0x07 0x7b
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# CHECK: entsp 1
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0x41 0x77
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# CHECK: entsp 70
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0x01 0xf0 0x46 0x77
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# CHECK: ldaw r11, cp[5]
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0x45 0x7f
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# CHECK: ldaw r11, cp[33000]
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0x03 0xf2 0x68 0x7f
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# CHECK: retsp 40
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0xe8 0x77
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|
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# CHECK: retsp 52010
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0x2c 0xf3 0xea 0x77
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|
|
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# CHECK: setsr 42
|
|
0x6a 0x7b
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|
|
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# CHECK: setsr 21863
|
|
0x55 0xf1 0x67 0x7b
|
|
|
|
# CHECK: extdp 4
|
|
0x84 0x73
|
|
|
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# CHECK: extdp 554
|
|
0x08 0xf0 0xaa 0x73
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|
|
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# CHECK: blat 9
|
|
0x49 0x73
|
|
|
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# CHECK: blat 61212
|
|
0xbc 0xf3 0x5c 0x73
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|
|
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# CHECK: getsr r11, 54
|
|
0x36 0x7f
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|
|
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# CHECK: getsr r11, 442
|
|
0x06 0xf0 0x3a 0x7f
|
|
|
|
# CHECK: kcall 11
|
|
0xcb 0x73
|
|
|
|
# CHECK: kcall 4001
|
|
0x3e 0xf0 0xe1 0x73
|
|
|
|
# CHECK: kentsp 22
|
|
0x96 0x7b
|
|
|
|
# CHECK: kentsp 8793
|
|
0x89 0xf0 0x99 0x7b
|
|
|
|
# CHECK: krestsp 0
|
|
0xc0 0x7b
|
|
|
|
# CHECK: krestsp 55312
|
|
0x60 0xf3 0xd0 0x7b
|
|
|
|
# u10 / lu10 instructions
|
|
|
|
# CHECK: ldap r11, 40
|
|
0x28 0xd8
|
|
|
|
# CHECK: ldap r11, 53112
|
|
0x33 0xf0 0x78 0xdb
|
|
|
|
# CHECK: ldap r11, -22
|
|
0x16 0xdc
|
|
|
|
# CHECK: ldap r11, -9999
|
|
0x09 0xf0 0x0f 0xdf
|
|
|
|
# CHECK: bl 8
|
|
0x08 0xd0
|
|
|
|
# CHECK: bl 38631
|
|
0x25 0xf0 0xe7 0xd2
|
|
|
|
# CHECK: bl -222
|
|
0xde 0xd4
|
|
|
|
# CHECK: bl -55132
|
|
0x35 0xf0 0x5c 0xd7
|
|
|
|
# CHECK: bla cp[500]
|
|
0xf4 0xe1
|
|
|
|
# CHECK: bla cp[413742]
|
|
0x94 0xf1 0x2e 0xe0
|
|
|
|
# CHECK: ldw r11, cp[132]
|
|
0x84 0xe4
|
|
|
|
# CHECK: ldw r11, cp[102741]
|
|
0x64 0xf0 0x55 0xe5
|
|
|
|
# l6r instructions
|
|
|
|
# CHECK: lmul r11, r0, r2, r5, r8, r10
|
|
0xf9 0xfa 0x02 0x06
|
|
|
|
# l5r instructions
|
|
|
|
# CHECK: ladd r10, r2, r5, r1, r7
|
|
0xe5 0xf8 0xfb 0x06
|
|
|
|
# CHECK: ldivu r5, r6, r3, r9, r8
|
|
0x54 0xfe 0x0b 0x07
|
|
|
|
# CHECK: lsub r1, r8, r7, r11, r5
|
|
0xcf 0xfd 0x85 0x0f
|
|
|
|
# l4r instructions
|
|
|
|
# CHECK: crc8 r6, r3, r4, r11
|
|
0x73 0xfd 0xe6 0x07
|
|
|
|
# CHECK: maccs r11, r8, r2, r4
|
|
0xf8 0xfa 0xe8 0x0f
|
|
|
|
# CHECK: maccu r0, r2, r5, r8
|
|
0x44 0xfd 0xf2 0x07
|