llvm-6502/test/CodeGen/Thumb2/thumb2-sxt_rot.ll
Tim Northover afb1938c39 ARM: spot SBFX-compatbile code expressed with sign_extend_inreg
We were assuming all SBFX-like operations would have the shl/asr form, but
often when the field being extracted is an i8 or i16, we end up with a
SIGN_EXTEND_INREG acting on a shift instead. Simple enough to check for though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213754 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-23 13:59:12 +00:00

43 lines
910 B
LLVM

; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2,+t2xtpk %s -o - \
; RUN: | FileCheck %s
define i32 @test0(i8 %A) {
; CHECK-LABEL: test0:
; CHECK: sxtb r0, r0
%B = sext i8 %A to i32
ret i32 %B
}
define signext i8 @test1(i32 %A) {
; CHECK-LABEL: test1:
; CHECK: sbfx r0, r0, #8, #8
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
%E = trunc i32 %D to i8
ret i8 %E
}
define signext i32 @test2(i32 %A, i32 %X) {
; CHECK-LABEL: test2:
; CHECK: sxtab r0, r1, r0, ror #8
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
%E = trunc i32 %D to i8
%F = sext i8 %E to i32
%G = add i32 %F, %X
ret i32 %G
}
define i32 @test3(i32 %A, i32 %X) {
; CHECK-LABEL: test3:
; CHECK: sxtah r0, r0, r1, ror #8
%X.hi = lshr i32 %X, 8
%X.trunc = trunc i32 %X.hi to i16
%addend = sext i16 %X.trunc to i32
%sum = add i32 %A, %addend
ret i32 %sum
}