llvm-6502/test/CodeGen
Elena Demikhovsky 189930760d AVX-512: Fixed a bug in comparison of i1 vectors.
cmp eq should give kxnor instruction
cmp neq should give kxor 

https://llvm.org/bugs/show_bug.cgi?id=23631



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239460 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-10 06:49:28 +00:00
..
AArch64 [AArch64] Remove an overly conservative check when generating store pairs. 2015-06-09 20:59:41 +00:00
ARM Add explicit -mtriple=arm-unknown to llvm/test/CodeGen/ARM/disable-tail-calls.ll, to satisfy *-win32. 2015-06-09 23:33:25 +00:00
BPF [bpf] rename triple names bpf_be -> bpfeb 2015-06-05 16:11:14 +00:00
CPP
Generic
Hexagon [Hexagon] Adding functionality for searching for compound instruction pairs. Compound instructions reduce slot resource requirements freeing those packet slots up for more instructions. 2015-06-08 16:34:47 +00:00
Inputs
Mips [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only. 2015-06-02 20:32:50 +00:00
MIR MIR Serialization: use correct line and column numbers for LLVM IR errors. 2015-05-29 17:05:41 +00:00
MSP430
NVPTX [NVPTX] fix a crash bug in NVPTXFavorNonGenericAddrSpaces 2015-06-09 21:50:32 +00:00
PowerPC Add support for VSX FMA single-precision instructions to the PPC back end 2015-05-29 17:13:25 +00:00
R600 Implement computeKnownBits for min/max nodes 2015-06-09 00:52:41 +00:00
SPARC
SystemZ
Thumb Revert r238473, "Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM." 2015-06-05 18:01:28 +00:00
Thumb2 ARM: Thumb2 LDRD/STRD supports independent input/output regs 2015-06-03 16:30:24 +00:00
WinEH
X86 AVX-512: Fixed a bug in comparison of i1 vectors. 2015-06-10 06:49:28 +00:00
XCore