Evan Cheng 189c1ec4c1 Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117745 91177308-0d34-0410-b5e6-96231b3b80d8		2010-10-29 23:36:03 +00:00
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Alpha
ARM	Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857.	2010-10-29 23:36:03 +00:00
Blackfin
CBackend
CellSPU	Change v64 datalayout in SPU.	2010-10-26 10:45:47 +00:00
CPP
Generic
MBlaze	Recommit 116986 with capitalization typo fixed.	2010-10-21 03:57:26 +00:00
Mips	Enable machine sinking critical edge splitting. e.g.	2010-09-20 22:52:00 +00:00
MSP430	CombinerAA is now reordering these stores.	2010-09-20 20:56:29 +00:00
PowerPC	PowerPC varargs functions store live-in registers on the stack. Make sure we use	2010-10-11 20:43:09 +00:00
PTX	Add test case mov.ll for PTX device function	2010-10-19 13:21:51 +00:00
SPARC
SystemZ	Correct bogus module triple specifications.	2010-08-30 10:48:29 +00:00
Thumb	Try again to disable critical edge splitting in CodeGenPrepare.	2010-09-30 20:51:52 +00:00
Thumb2	Avoiding overly aggressive latency scheduling. If the two nodes share an	2010-10-29 18:09:28 +00:00
X86	Fix pastos in handling of AVX cvttsd2si, PR8491.	2010-10-28 00:35:54 +00:00
XCore	Enable machine sinking critical edge splitting. e.g.	2010-09-20 22:52:00 +00:00
thumb2-mul.ll	Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes	2010-09-21 22:51:46 +00:00