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https://github.com/c64scene-ar/llvm-6502.git
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8fc760cbe8
My recent ARM FastISel patch exposed this bug: http://llvm.org/bugs/show_bug.cgi?id=16178 The root cause is that it can't select integer sext/zext pre-ARMv6 and asserts out. The current integer sext/zext code doesn't handle other cases gracefully either, so this patch makes it handle all sext and zext from i1/i8/i16 to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This should fix the bug as well as make FastISel faster because it bails to SelectionDAG less often. See fastisel-ext.patch for this. fastisel-ext-tests.patch changes current tests to always use reg-imm AND for 8-bit zext instead of UXTB. This simplifies code since it is supported on ARMv4t and later, and at least on A15 both should perform exactly the same (both have exec 1 uop 1, type I). 2013-05-31-char-shift-crash.ll is a bitcode version of the above bug 16178 repro. fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel should now handle. Note that my ARM FastISel enabling patch was reverted due to a separate failure when dealing with MCJIT, I'll fix this second failure and then turn FastISel on again for non-iOS ARM targets. I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15 hardware. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183551 91177308-0d34-0410-b5e6-96231b3b80d8
85 lines
1.7 KiB
LLVM
85 lines
1.7 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
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@a = global i8 1, align 1
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@b = global i16 2, align 2
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define void @t1() nounwind uwtable ssp {
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; ARM: t1
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; ARM: ldrb
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; ARM-NOT: uxtb
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; ARM-NOT: and{{.*}}, #255
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; THUMB: t1
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; THUMB: ldrb
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; THUMB-NOT: uxtb
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; THUMB-NOT: and{{.*}}, #255
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%1 = load i8* @a, align 1
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call void @foo1(i8 zeroext %1)
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ret void
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}
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define void @t2() nounwind uwtable ssp {
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; ARM: t2
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; ARM: ldrh
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; ARM-NOT: uxth
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; THUMB: t2
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; THUMB: ldrh
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; THUMB-NOT: uxth
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%1 = load i16* @b, align 2
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call void @foo2(i16 zeroext %1)
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ret void
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}
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declare void @foo1(i8 zeroext)
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declare void @foo2(i16 zeroext)
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define i32 @t3() nounwind uwtable ssp {
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; ARM: t3
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; ARM: ldrb
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; ARM-NOT: uxtb
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; ARM-NOT: and{{.*}}, #255
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; THUMB: t3
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; THUMB: ldrb
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; THUMB-NOT: uxtb
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; THUMB-NOT: and{{.*}}, #255
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%1 = load i8* @a, align 1
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%2 = zext i8 %1 to i32
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ret i32 %2
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}
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define i32 @t4() nounwind uwtable ssp {
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; ARM: t4
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; ARM: ldrh
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; ARM-NOT: uxth
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; THUMB: t4
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; THUMB: ldrh
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; THUMB-NOT: uxth
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%1 = load i16* @b, align 2
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%2 = zext i16 %1 to i32
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ret i32 %2
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}
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define i32 @t5() nounwind uwtable ssp {
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; ARM: t5
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; ARM: ldrsh
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; ARM-NOT: sxth
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; THUMB: t5
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; THUMB: ldrsh
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; THUMB-NOT: sxth
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%1 = load i16* @b, align 2
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%2 = sext i16 %1 to i32
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ret i32 %2
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}
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define i32 @t6() nounwind uwtable ssp {
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; ARM: t6
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; ARM: ldrsb
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; ARM-NOT: sxtb
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; THUMB: t6
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; THUMB: ldrsb
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; THUMB-NOT: sxtb
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%1 = load i8* @a, align 2
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%2 = sext i8 %1 to i32
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ret i32 %2
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}
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