Tom Stellard 19301d5d12 R600: Expand vector or, shl, srl, and xor nodes ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181035 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-03 17:21:31 +00:00
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AArch64
ARM
CPP
Generic
Hexagon	Hexagon - Add peephole optimizations for zero extends.	2013-05-02 20:22:51 +00:00
Inputs
MBlaze
Mips	[mips] Handle reading, writing or copying of ccond field of DSP control	2013-05-02 23:07:05 +00:00
MSP430
NVPTX
PowerPC
R600	R600: Expand vector or, shl, srl, and xor nodes	2013-05-03 17:21:31 +00:00
SI
SPARC
Thumb
Thumb2
X86	TBAA: remove !tbaa from testing cases if not used.	2013-05-02 18:11:35 +00:00
XCore