Scott Michel 1a6cdb6b50 CellSPU: ... - Fix v2[if]64 vector insertion code before IBM files a bug report. - Ensure that zero (0) offsets relative to $sp don't trip an assert (add $sp, 0 gets legalized to $sp alone, tripping an assert) - Shuffle masks passed to SPUISD::SHUFB are now v16i8 or v4i32 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60358 91177308-0d34-0410-b5e6-96231b3b80d8		2008-12-01 17:56:02 +00:00
..
Alpha	Correct some thinkos in the expansion of ADD/SUB	2008-11-12 08:23:26 +00:00
ARM	- Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction.	2008-11-20 02:32:35 +00:00
CBackend	Fix PR2907 by digging through constant expressions to find FP constants that	2008-10-22 04:53:16 +00:00
CellSPU	CellSPU:	2008-12-01 17:56:02 +00:00
CPP	Put CPPBackend tests into their own directory and run them only if they're	2008-07-10 22:35:32 +00:00
Generic	Test add-with-overflow with fast ISel.	2008-11-24 05:23:38 +00:00
IA64
Mips	Fix PR2667: add soft float support for sint_to_fp/uint_to_fp	2008-11-10 17:36:26 +00:00
PowerPC	Check that running the DAG combiner between type	2008-11-26 16:44:30 +00:00
SPARC	Add testcase for 'r' inline asm operand	2008-10-10 20:28:59 +00:00
X86	Followup to r60283: optimize arbitrary width signed divisions as well	2008-11-30 06:35:39 +00:00
XCore	Reapply r59464, this time using the correct type	2008-11-18 09:15:03 +00:00