Hal Finkel 0ef8f3189e [PowerPC] Enable speculation of cttz/ctlz ... PPC has an instruction for ctlz with defined zero behavior, and our lowering of cttz (provided by DAGCombine) is also efficient and branchless, so speculating these makes sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225150 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-05 05:24:42 +00:00
..
AArch64	Lower multiply-negate operation to mneg on AArch64	2014-12-22 13:38:58 +00:00
ARM	ARM: permit tail calls to weak externals on COFF	2015-01-03 21:35:00 +00:00
CPP
Generic	CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.	2014-12-19 20:50:07 +00:00
Hexagon	[Hexagon] Adding reg-reg indexed load forms.	2014-12-30 18:58:47 +00:00
Inputs	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Mips	[mips][microMIPS] Fix bugs related to atomic SC/LL instructions	2014-12-18 16:39:29 +00:00
MSP430
NVPTX	[NVPTX] Fix bugs related to isSingleValueType	2014-12-17 17:59:04 +00:00
PowerPC	[PowerPC] Enable speculation of cttz/ctlz	2015-01-05 05:24:42 +00:00
R600	Enable (sext x) == C --> x == (trunc C) combine	2014-12-21 16:48:42 +00:00
SPARC	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
SystemZ	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb2	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
X86	[X86][SSE] Added vector packing test for pr12412	2015-01-04 19:08:03 +00:00
XCore	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00