mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-30 05:29:47 +00:00
8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
91 lines
3.3 KiB
LLVM
91 lines
3.3 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
|
|
|
|
declare i32 @llvm.r600.read.tidig.x() #1
|
|
|
|
; Test with inline immediate
|
|
|
|
; FUNC-LABEL: {{^}}shl_2_add_9_i32:
|
|
; SI: v_lshlrev_b32_e32 [[REG:v[0-9]+]], 2, {{v[0-9]+}}
|
|
; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], 36, [[REG]]
|
|
; SI: buffer_store_dword [[RESULT]]
|
|
; SI: s_endpgm
|
|
define void @shl_2_add_9_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
|
%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
|
|
%ptr = getelementptr i32 addrspace(1)* %in, i32 %tid.x
|
|
%val = load i32 addrspace(1)* %ptr, align 4
|
|
%add = add i32 %val, 9
|
|
%result = shl i32 %add, 2
|
|
store i32 %result, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}shl_2_add_9_i32_2_add_uses:
|
|
; SI-DAG: v_add_i32_e32 [[ADDREG:v[0-9]+]], 9, {{v[0-9]+}}
|
|
; SI-DAG: v_lshlrev_b32_e32 [[SHLREG:v[0-9]+]], 2, {{v[0-9]+}}
|
|
; SI-DAG: buffer_store_dword [[ADDREG]]
|
|
; SI-DAG: buffer_store_dword [[SHLREG]]
|
|
; SI: s_endpgm
|
|
define void @shl_2_add_9_i32_2_add_uses(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %in) #0 {
|
|
%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
|
|
%ptr = getelementptr i32 addrspace(1)* %in, i32 %tid.x
|
|
%val = load i32 addrspace(1)* %ptr, align 4
|
|
%add = add i32 %val, 9
|
|
%result = shl i32 %add, 2
|
|
store i32 %result, i32 addrspace(1)* %out0, align 4
|
|
store i32 %add, i32 addrspace(1)* %out1, align 4
|
|
ret void
|
|
}
|
|
|
|
; Test with add literal constant
|
|
|
|
; FUNC-LABEL: {{^}}shl_2_add_999_i32:
|
|
; SI: v_lshlrev_b32_e32 [[REG:v[0-9]+]], 2, {{v[0-9]+}}
|
|
; SI: v_add_i32_e32 [[RESULT:v[0-9]+]], 0xf9c, [[REG]]
|
|
; SI: buffer_store_dword [[RESULT]]
|
|
; SI: s_endpgm
|
|
define void @shl_2_add_999_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
|
|
%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
|
|
%ptr = getelementptr i32 addrspace(1)* %in, i32 %tid.x
|
|
%val = load i32 addrspace(1)* %ptr, align 4
|
|
%shl = add i32 %val, 999
|
|
%result = shl i32 %shl, 2
|
|
store i32 %result, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}test_add_shl_add_constant:
|
|
; SI-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
|
|
; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
|
|
; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3
|
|
; SI: s_add_i32 [[TMP:s[0-9]+]], [[SHL3]], [[Y]]
|
|
; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8
|
|
; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
|
|
; SI: buffer_store_dword [[VRESULT]]
|
|
define void @test_add_shl_add_constant(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {
|
|
%add.0 = add i32 %x, 123
|
|
%shl = shl i32 %add.0, 3
|
|
%add.1 = add i32 %shl, %y
|
|
store i32 %add.1, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}test_add_shl_add_constant_inv:
|
|
; SI-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
|
|
; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
|
|
; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3
|
|
; SI: s_add_i32 [[TMP:s[0-9]+]], [[SHL3]], [[Y]]
|
|
; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8
|
|
; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]]
|
|
; SI: buffer_store_dword [[VRESULT]]
|
|
|
|
define void @test_add_shl_add_constant_inv(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 {
|
|
%add.0 = add i32 %x, 123
|
|
%shl = shl i32 %add.0, 3
|
|
%add.1 = add i32 %y, %shl
|
|
store i32 %add.1, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind readnone }
|