mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
51 lines
1.5 KiB
LLVM
51 lines
1.5 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; Test that we correctly commute a sub instruction
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; FUNC-LABEL: {{^}}sub_rev:
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; SI-NOT: v_sub_i32_e32 v{{[0-9]+}}, s
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; SI: v_subrev_i32_e32 v{{[0-9]+}}, s
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; ModuleID = 'vop-shrink.ll'
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define void @sub_rev(i32 addrspace(1)* %out, <4 x i32> %sgpr, i32 %cond) {
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entry:
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%vgpr = call i32 @llvm.r600.read.tidig.x() #1
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%tmp = icmp eq i32 %cond, 0
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br i1 %tmp, label %if, label %else
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if: ; preds = %entry
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%tmp1 = getelementptr i32 addrspace(1)* %out, i32 1
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%tmp2 = extractelement <4 x i32> %sgpr, i32 1
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store i32 %tmp2, i32 addrspace(1)* %out
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br label %endif
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else: ; preds = %entry
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%tmp3 = extractelement <4 x i32> %sgpr, i32 2
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%tmp4 = sub i32 %vgpr, %tmp3
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store i32 %tmp4, i32 addrspace(1)* %out
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br label %endif
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endif: ; preds = %else, %if
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ret void
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}
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; Test that we fold an immediate that was illegal for a 64-bit op into the
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; 32-bit op when we shrink it.
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; FUNC-LABEL: {{^}}add_fold:
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; SI: v_add_f32_e32 v{{[0-9]+}}, 0x44800000
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define void @add_fold(float addrspace(1)* %out) {
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entry:
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%tmp = call i32 @llvm.r600.read.tidig.x()
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%tmp1 = uitofp i32 %tmp to float
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%tmp2 = fadd float %tmp1, 1.024000e+03
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store float %tmp2, float addrspace(1)* %out
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.r600.read.tidig.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { readnone }
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