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https://github.com/c64scene-ar/llvm-6502.git
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8b2b8a1835
This update was done with the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
fi
done
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
166 lines
4.2 KiB
LLVM
166 lines
4.2 KiB
LLVM
; Test 128-bit addition in which the second operand is a zero-extended i32.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check register additions. The XOR ensures that we don't instead zero-extend
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; %b into a register and use memory addition.
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define void @f1(i128 *%aptr, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: slgfr {{%r[0-5]}}, %r3
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Like f1, but using an "in-register" extension.
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define void @f2(i128 *%aptr, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: slgfr {{%r[0-5]}}, %r3
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%trunc = trunc i64 %b to i32
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%bext = zext i32 %trunc to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Test register addition in cases where the second operand is zero extended
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; from i64 rather than i32, but is later masked to i32 range.
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define void @f3(i128 *%aptr, i64 %b) {
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; CHECK-LABEL: f3:
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; CHECK: slgfr {{%r[0-5]}}, %r3
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%bext = zext i64 %b to i128
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%and = and i128 %bext, 4294967295
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%sub = sub i128 %xor, %and
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Test SLGF with no offset.
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define void @f4(i128 *%aptr, i32 *%bsrc) {
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; CHECK-LABEL: f4:
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; CHECK: slgf {{%r[0-5]}}, 0(%r3)
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%b = load i32 *%bsrc
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Check the high end of the SLGF range.
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define void @f5(i128 *%aptr, i32 *%bsrc) {
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; CHECK-LABEL: f5:
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; CHECK: slgf {{%r[0-5]}}, 524284(%r3)
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%ptr = getelementptr i32 *%bsrc, i64 131071
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%b = load i32 *%ptr
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Check the next word up, which must use separate address logic.
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; Other sequences besides this one would be OK.
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define void @f6(i128 *%aptr, i32 *%bsrc) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r3, 524288
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; CHECK: slgf {{%r[0-5]}}, 0(%r3)
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%ptr = getelementptr i32 *%bsrc, i64 131072
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%b = load i32 *%ptr
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Check the high end of the negative aligned SLGF range.
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define void @f7(i128 *%aptr, i32 *%bsrc) {
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; CHECK-LABEL: f7:
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; CHECK: slgf {{%r[0-5]}}, -4(%r3)
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%ptr = getelementptr i32 *%bsrc, i128 -1
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%b = load i32 *%ptr
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Check the low end of the SLGF range.
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define void @f8(i128 *%aptr, i32 *%bsrc) {
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; CHECK-LABEL: f8:
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; CHECK: slgf {{%r[0-5]}}, -524288(%r3)
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%ptr = getelementptr i32 *%bsrc, i128 -131072
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%b = load i32 *%ptr
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f9(i128 *%aptr, i32 *%bsrc) {
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; CHECK-LABEL: f9:
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; CHECK: agfi %r3, -524292
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; CHECK: slgf {{%r[0-5]}}, 0(%r3)
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%ptr = getelementptr i32 *%bsrc, i128 -131073
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%b = load i32 *%ptr
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Check that SLGF allows an index.
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define void @f10(i128 *%aptr, i64 %src, i64 %index) {
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; CHECK-LABEL: f10:
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; CHECK: slgf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524284
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32 *%ptr
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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