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https://github.com/c64scene-ar/llvm-6502.git
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36e91e9599
expand offsets that do not fit in the 16-bit immediate field of load and store instructions. Also change the types of variables so that they are sufficiently large to handle 64-bit pointers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148916 91177308-0d34-0410-b5e6-96231b3b80d8
283 lines
10 KiB
C++
283 lines
10 KiB
C++
//===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MIPS implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-reg-info"
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#include "Mips.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsSubtarget.h"
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#include "MipsRegisterInfo.h"
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#include "MipsMachineFunction.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Analysis/DebugInfo.h"
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#define GET_REGINFO_TARGET_DESC
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#include "MipsGenRegisterInfo.inc"
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using namespace llvm;
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MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
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const TargetInstrInfo &tii)
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: MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
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unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
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//===----------------------------------------------------------------------===//
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// Callee Saved Registers methods
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//===----------------------------------------------------------------------===//
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/// Mips Callee Saved Registers
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const unsigned* MipsRegisterInfo::
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getCalleeSavedRegs(const MachineFunction *MF) const
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{
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// Mips callee-save register range is $16-$23, $f20-$f30
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static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
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Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26,
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Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20,
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Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
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Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
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};
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static const unsigned Mips32CalleeSavedRegs[] = {
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Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10,
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Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
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Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
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};
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static const unsigned N32CalleeSavedRegs[] = {
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Mips::D31_64, Mips::D29_64, Mips::D27_64, Mips::D25_64, Mips::D23_64,
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Mips::D21_64,
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Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64,
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Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64,
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Mips::S0_64, 0
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};
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static const unsigned N64CalleeSavedRegs[] = {
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Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64,
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Mips::D26_64, Mips::D25_64, Mips::D24_64,
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Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64,
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Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64,
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Mips::S0_64, 0
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};
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if (Subtarget.isSingleFloat())
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return SingleFloatOnlyCalleeSavedRegs;
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else if (!Subtarget.hasMips64())
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return Mips32CalleeSavedRegs;
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else if (Subtarget.isABI_N32())
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return N32CalleeSavedRegs;
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assert(Subtarget.isABI_N64());
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return N64CalleeSavedRegs;
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}
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BitVector MipsRegisterInfo::
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getReservedRegs(const MachineFunction &MF) const {
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static const unsigned ReservedCPURegs[] = {
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Mips::ZERO, Mips::AT, Mips::K0, Mips::K1,
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Mips::GP, Mips::SP, Mips::FP, Mips::RA
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};
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static const unsigned ReservedCPU64Regs[] = {
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Mips::ZERO_64, Mips::AT_64, Mips::K0_64, Mips::K1_64,
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Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64
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};
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BitVector Reserved(getNumRegs());
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typedef TargetRegisterClass::iterator RegIter;
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for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I)
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Reserved.set(ReservedCPURegs[I]);
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if (Subtarget.hasMips64()) {
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for (unsigned I = 0; I < array_lengthof(ReservedCPU64Regs); ++I)
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Reserved.set(ReservedCPU64Regs[I]);
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// Reserve all registers in AFGR64.
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for (RegIter Reg = Mips::AFGR64RegisterClass->begin();
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Reg != Mips::AFGR64RegisterClass->end(); ++Reg)
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Reserved.set(*Reg);
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}
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else {
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// Reserve all registers in CPU64Regs & FGR64.
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for (RegIter Reg = Mips::CPU64RegsRegisterClass->begin();
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Reg != Mips::CPU64RegsRegisterClass->end(); ++Reg)
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Reserved.set(*Reg);
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for (RegIter Reg = Mips::FGR64RegisterClass->begin();
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Reg != Mips::FGR64RegisterClass->end(); ++Reg)
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Reserved.set(*Reg);
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}
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return Reserved;
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}
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// This function eliminate ADJCALLSTACKDOWN,
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// ADJCALLSTACKUP pseudo instructions
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void MipsRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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// Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
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MBB.erase(I);
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}
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// FrameIndex represent objects inside a abstract stack.
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// We must replace FrameIndex with an stack/frame pointer
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// direct reference.
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void MipsRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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RegScavenger *RS) const {
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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unsigned i = 0;
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() &&
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"Instr doesn't have FrameIndex operand!");
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}
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DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
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errs() << "<--------->\n" << MI);
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int FrameIndex = MI.getOperand(i).getIndex();
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uint64_t stackSize = MF.getFrameInfo()->getStackSize();
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int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
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<< "spOffset : " << spOffset << "\n"
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<< "stackSize : " << stackSize << "\n");
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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int MinCSFI = 0;
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int MaxCSFI = -1;
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if (CSI.size()) {
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MinCSFI = CSI[0].getFrameIdx();
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MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
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}
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// The following stack frame objects are always referenced relative to $sp:
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// 1. Outgoing arguments.
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// 2. Pointer to dynamically allocated stack space.
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// 3. Locations for callee-saved registers.
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// Everything else is referenced relative to whatever register
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// getFrameRegister() returns.
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unsigned FrameReg;
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if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
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(FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
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FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
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else
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FrameReg = getFrameRegister(MF);
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// Calculate final offset.
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// - There is no need to change the offset if the frame object is one of the
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// following: an outgoing argument, pointer to a dynamically allocated
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// stack space or a $gp restore location,
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// - If the frame object is any of the following, its offset must be adjusted
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// by adding the size of the stack:
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// incoming argument, callee-saved register location or local variable.
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int64_t Offset;
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if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
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MipsFI->isDynAllocFI(FrameIndex))
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Offset = spOffset;
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else
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Offset = spOffset + (int64_t)stackSize;
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Offset += MI.getOperand(i+1).getImm();
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DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
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// If MI is not a debug value, make sure Offset fits in the 16-bit immediate
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// field.
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if (!MI.isDebugValue() && !isInt<16>(Offset)) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = II->getDebugLoc();
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MipsAnalyzeImmediate AnalyzeImm;
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unsigned Size = Subtarget.isABI_N64() ? 64 : 32;
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unsigned LUi = Subtarget.isABI_N64() ? Mips::LUi64 : Mips::LUi;
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unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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unsigned ZEROReg = Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ATReg = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT;
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const MipsAnalyzeImmediate::InstSeq &Seq =
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AnalyzeImm.Analyze(Offset, Size, true /* LastInstrIsADDiu */);
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MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
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// FIXME: change this when mips goes MC".
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BuildMI(MBB, II, DL, TII.get(Mips::NOAT));
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// The first instruction can be a LUi, which is different from other
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// instructions (ADDiu, ORI and SLL) in that it does not have a register
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// operand.
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if (Inst->Opc == LUi)
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BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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else
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BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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// Build the remaining instructions in Seq except for the last one.
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for (++Inst; Inst != Seq.end() - 1; ++Inst)
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BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(ATReg);
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FrameReg = ATReg;
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Offset = SignExtend64<16>(Inst->ImmOpnd);
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BuildMI(MBB, ++II, MI.getDebugLoc(), TII.get(Mips::ATMACRO));
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}
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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}
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unsigned MipsRegisterInfo::
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getFrameRegister(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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bool IsN64 = Subtarget.isABI_N64();
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return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) :
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(IsN64 ? Mips::SP_64 : Mips::SP);
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}
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unsigned MipsRegisterInfo::
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getEHExceptionRegister() const {
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llvm_unreachable("What is the exception register");
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}
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unsigned MipsRegisterInfo::
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getEHHandlerRegister() const {
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llvm_unreachable("What is the exception handler register");
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}
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