llvm-6502/lib/Target/Alpha
Evan Cheng ffc0e73046 Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09 05:47:46 +00:00
..
TargetInfo
Alpha.h Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc 2011-06-28 20:07:07 +00:00
Alpha.td Fix a ton of comment typos found by codespell. Patch by 2011-04-15 05:18:47 +00:00
AlphaAsmPrinter.cpp
AlphaBranchSelector.cpp
AlphaCallingConv.td
AlphaFrameLowering.cpp
AlphaFrameLowering.h
AlphaInstrFormats.td
AlphaInstrInfo.cpp Hide the call to InitMCInstrInfo into tblgen generated ctor. 2011-07-01 17:57:27 +00:00
AlphaInstrInfo.h Hide the call to InitMCInstrInfo into tblgen generated ctor. 2011-07-01 17:57:27 +00:00
AlphaInstrInfo.td Fix a ton of comment typos found by codespell. Patch by 2011-04-15 05:18:47 +00:00
AlphaISelDAGToDAG.cpp
AlphaISelLowering.cpp Add an intrinsic and codegen support for fused multiply-accumulate. The intent 2011-07-08 21:39:21 +00:00
AlphaISelLowering.h Move Alpha from getRegClassForInlineAsmConstraint to 2011-06-29 19:40:01 +00:00
AlphaLLRP.cpp
AlphaMachineFunctionInfo.h
AlphaMCAsmInfo.cpp
AlphaMCAsmInfo.h
AlphaRegisterInfo.cpp Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. 2011-06-28 21:14:33 +00:00
AlphaRegisterInfo.h Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc 2011-06-27 18:32:37 +00:00
AlphaRegisterInfo.td Use set operations instead of plain lists to enumerate register classes. 2011-06-15 23:28:14 +00:00
AlphaRelocations.h
AlphaSchedule.td
AlphaSelectionDAGInfo.cpp
AlphaSelectionDAGInfo.h
AlphaSubtarget.cpp Change createAsmParser to take a MCSubtargetInfo instead of triple, 2011-07-09 05:47:46 +00:00
AlphaSubtarget.h Compute feature bits at time of MCSubtargetInfo initialization. 2011-07-07 07:07:08 +00:00
AlphaTargetMachine.cpp Eliminate asm parser's dependency on TargetMachine: 2011-07-08 01:53:10 +00:00
AlphaTargetMachine.h Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to 2011-06-30 01:53:36 +00:00
CMakeLists.txt Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency. 2011-07-01 22:36:09 +00:00
Makefile Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency. 2011-07-01 22:36:09 +00:00
README.txt Fix a ton of comment typos found by codespell. Patch by 2011-04-15 05:18:47 +00:00

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum across bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extensions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html