1
0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 20:29:48 +00:00
llvm-6502/test/CodeGen/X86/v2f32.ll
Nico Rieck 3c1dc3cac8 Fix non-deterministic SDNodeOrder-dependent codegen
Reset SelectionDAGBuilder's SDNodeOrder to ensure deterministic code
generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199050 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-12 14:09:17 +00:00

116 lines
2.8 KiB
LLVM

; RUN: llc < %s -mtriple=x86_64-linux -mcpu=penryn -asm-verbose=0 -o - | FileCheck %s -check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=penryn -asm-verbose=0 -o - | FileCheck %s -check-prefix=W64
; RUN: llc < %s -mcpu=yonah -march=x86 -mtriple=i386-linux-gnu -asm-verbose=0 -o - | FileCheck %s -check-prefix=X32
; PR7518
define void @test1(<2 x float> %Q, float *%P2) nounwind {
%a = extractelement <2 x float> %Q, i32 0
%b = extractelement <2 x float> %Q, i32 1
%c = fadd float %a, %b
store float %c, float* %P2
ret void
; X64-LABEL: test1:
; X64-NEXT: pshufd $1, %xmm0, %xmm1
; X64-NEXT: addss %xmm0, %xmm1
; X64-NEXT: movss %xmm1, (%rdi)
; X64-NEXT: ret
; W64-LABEL: test1:
; W64-NEXT: movdqa (%rcx), %xmm0
; W64-NEXT: pshufd $1, %xmm0, %xmm1
; W64-NEXT: addss %xmm0, %xmm1
; W64-NEXT: movss %xmm1, (%rdx)
; W64-NEXT: ret
; X32-LABEL: test1:
; X32-NEXT: movl 4(%esp), %eax
; X32-NEXT: pshufd $1, %xmm0, %xmm1
; X32-NEXT: addss %xmm0, %xmm1
; X32-NEXT: movss %xmm1, (%eax)
; X32-NEXT: ret
}
define <2 x float> @test2(<2 x float> %Q, <2 x float> %R, <2 x float> *%P) nounwind {
%Z = fadd <2 x float> %Q, %R
ret <2 x float> %Z
; X64-LABEL: test2:
; X64-NEXT: addps %xmm1, %xmm0
; X64-NEXT: ret
; W64-LABEL: test2:
; W64-NEXT: movaps (%rcx), %xmm0
; W64-NEXT: addps (%rdx), %xmm0
; W64-NEXT: ret
; X32-LABEL: test2:
; X32: addps %xmm1, %xmm0
}
define <2 x float> @test3(<4 x float> %A) nounwind {
%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
%C = fadd <2 x float> %B, %B
ret <2 x float> %C
; X64-LABEL: test3:
; X64-NEXT: addps %xmm0, %xmm0
; X64-NEXT: ret
; W64-LABEL: test3:
; W64-NEXT: movaps (%rcx), %xmm0
; W64-NEXT: addps %xmm0, %xmm0
; W64-NEXT: ret
; X32-LABEL: test3:
; X32-NEXT: addps %xmm0, %xmm0
; X32-NEXT: ret
}
define <2 x float> @test4(<2 x float> %A) nounwind {
%C = fadd <2 x float> %A, %A
ret <2 x float> %C
; X64-LABEL: test4:
; X64-NEXT: addps %xmm0, %xmm0
; X64-NEXT: ret
; W64-LABEL: test4:
; W64-NEXT: movaps (%rcx), %xmm0
; W64-NEXT: addps %xmm0, %xmm0
; W64-NEXT: ret
; X32-LABEL: test4:
; X32-NEXT: addps %xmm0, %xmm0
; X32-NEXT: ret
}
define <4 x float> @test5(<4 x float> %A) nounwind {
%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
%C = fadd <2 x float> %B, %B
br label %BB
BB:
%D = fadd <2 x float> %C, %C
%E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %E
; X64-LABEL: test5:
; X64-NEXT: addps %xmm0, %xmm0
; X64-NEXT: addps %xmm0, %xmm0
; X64-NEXT: ret
; W64-LABEL: test5:
; W64-NEXT: movaps (%rcx), %xmm0
; W64-NEXT: addps %xmm0, %xmm0
; W64-NEXT: addps %xmm0, %xmm0
; W64-NEXT: ret
; X32-LABEL: test5:
; X32-NEXT: addps %xmm0, %xmm0
; X32-NEXT: addps %xmm0, %xmm0
; X32-NEXT: ret
}