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the internals of TargetMachine could change. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
52 lines
1.4 KiB
C++
52 lines
1.4 KiB
C++
//===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SIRegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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using namespace llvm;
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SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm)
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: AMDGPURegisterInfo(tm),
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TM(tm)
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{ }
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BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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return Reserved;
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}
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unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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return RC->getNumRegs();
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}
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const TargetRegisterClass *
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SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
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switch (rc->getID()) {
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case AMDGPU::GPRF32RegClassID:
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return &AMDGPU::VReg_32RegClass;
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default: return rc;
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}
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}
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const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
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MVT VT) const {
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switch(VT.SimpleTy) {
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default:
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case MVT::i32: return &AMDGPU::VReg_32RegClass;
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}
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}
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