Silviu Baranga 1c01249191 Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154101 91177308-0d34-0410-b5e6-96231b3b80d8		2012-04-05 16:19:29 +00:00
..
Analysis	Always compute all the bits in ComputeMaskedBits.	2012-04-04 12:51:34 +00:00
Archive
AsmParser
Bitcode
CodeGen	REG_SEQUENCE expansion to COPY instructions wasn't taking account of sub register indices on the source registers. No simple test case	2012-04-04 21:03:25 +00:00
DebugInfo	Fix a C++11 UDL conflict.	2012-04-04 20:33:56 +00:00
ExecutionEngine	Removing a file that's no longer being used after the recent refactorings	2012-04-01 06:50:01 +00:00
Linker
MC	Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter.	2012-04-02 08:32:38 +00:00
Object	Object: drop bogus VMCore dependency	2012-04-03 15:48:10 +00:00
Support	In MemoryBuffer::getOpenFile() make sure that the buffer is null-terminated if	2012-04-05 04:23:56 +00:00
TableGen
Target	Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.	2012-04-05 16:19:29 +00:00
Transforms	BBVectorize: Add the const modifier to the VectorizeConfig because we won't	2012-04-05 16:07:49 +00:00
VMCore	The speedup doesn't appear to have been from this, but was an anomaly of my testing machine.	2012-04-03 11:19:21 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile