Kalle Raiskila 1cd1b0b283 Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction. ... This cleans up after the mess r108567 left in the CellSPU backend. ORCvt-instruction were used to reinterpret registers, and the ORs were then removed by isMoveInstr(). This patch now removes 350 instrucions of format: or $3, $3, $3 (from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is checked for. Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114074 91177308-0d34-0410-b5e6-96231b3b80d8		2010-09-16 12:29:33 +00:00
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Alpha	PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually	2010-08-01 21:13:28 +00:00
ARM	Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem	2010-09-15 17:12:08 +00:00
Blackfin	Remove TargetInstrInfo::copyRegToReg entirely.	2010-07-11 17:01:17 +00:00
CBackend
CellSPU	Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.	2010-09-16 12:29:33 +00:00
CPP
Generic	Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself	2010-07-27 18:02:18 +00:00
MBlaze
Mips	Correct bogus module triple specifications.	2010-08-30 10:48:29 +00:00
MSP430
PIC16
PowerPC	PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.	2010-08-02 00:18:19 +00:00
SPARC
SystemZ	Correct bogus module triple specifications.	2010-08-30 10:48:29 +00:00
Thumb	Re-enable usage of the ARM base pointer. r113394 fixed the known failures.	2010-09-08 20:12:02 +00:00
Thumb2	Teach if-converter to be more careful with predicating instructions that would	2010-09-10 01:29:16 +00:00
X86	Add one more pattern to fallback movddup	2010-09-09 18:48:34 +00:00
XCore