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llvm-6502/test/CodeGen
History
Cameron McInally 1d5e37946d Fix bad copy-and-paste from r210652. AVX512 masked leading zero intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210901 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 13:20:01 +00:00
..
AArch64
[AArch64] Basic Sched Model for Cortex-A57.
2014-06-11 21:06:56 +00:00
ARM
CodeGen: enable mov.w/mov.t pairs with minsize for WoA
2014-06-12 20:06:33 +00:00
CPP
CPP backend: set volatile property on atomic instructions.
2014-06-13 09:14:50 +00:00
Generic
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Hexagon
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Inputs
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Mips
[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6
2014-06-12 15:00:17 +00:00
MSP430
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NVPTX
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PowerPC
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R600
R600/SI: Fix selection error on i64 rotl / rotr.
2014-06-13 04:00:30 +00:00
SPARC
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SystemZ
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Thumb
ARM: Fix fastcc calling convention for Thumb1
2014-06-13 08:33:03 +00:00
Thumb2
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X86
Fix bad copy-and-paste from r210652. AVX512 masked leading zero intrinsics.
2014-06-13 13:20:01 +00:00
XCore
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