Renato Golin 1e173b7139 Revert "[ARM] Combine base-updating/post-incrementing vector load/stores." ... This reverts commit r223862, as it created a regression on the test-suite on test MultiSource/Benchmarks/Ptrdist/anagram by scrambling the order in which the words are shown. We'll investigate the issue and re-apply when safe. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224198 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-13 20:23:18 +00:00
..
AArch64
ARM	Revert "[ARM] Combine base-updating/post-incrementing vector load/stores."	2014-12-13 20:23:18 +00:00
CPP
Generic	Rename argument strings of codegen passes to avoid collisions with command line	2014-12-13 04:52:04 +00:00
Hexagon
Inputs
Mips	[mips] Enable code generation for MIPS-III.	2014-12-12 15:16:46 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add a DAGToDAG peephole to remove unnecessary zero-exts	2014-12-12 23:59:36 +00:00
R600	R600: Fix min/max matching problems with unordered compares	2014-12-12 02:30:37 +00:00
SPARC
SystemZ
Thumb
Thumb2	[ARMConstantIsland] Insert tbb/tbh optimization where previous jump table resided.	2014-12-12 23:27:40 +00:00
X86	[AVX512] Enabling bit logic lowering	2014-12-12 17:02:18 +00:00
XCore