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5eb308b944
necessary. Sometimes, live range splitting doesn't shrink the current interval, but simply changes some instructions to use a new interval. That makes the original more suitable for spilling. In this case, we don't need to duplicate the original. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110481 91177308-0d34-0410-b5e6-96231b3b80d8
469 lines
16 KiB
C++
469 lines
16 KiB
C++
//===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The inline spiller modifies the machine function directly instead of
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// inserting spills and restores in VirtRegMap.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "spiller"
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#include "Spiller.h"
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#include "SplitKit.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class InlineSpiller : public Spiller {
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MachineFunctionPass &pass_;
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MachineFunction &mf_;
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LiveIntervals &lis_;
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MachineLoopInfo &loops_;
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VirtRegMap &vrm_;
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MachineFrameInfo &mfi_;
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MachineRegisterInfo &mri_;
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const TargetInstrInfo &tii_;
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const TargetRegisterInfo &tri_;
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const BitVector reserved_;
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SplitAnalysis splitAnalysis_;
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// Variables that are valid during spill(), but used by multiple methods.
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LiveInterval *li_;
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std::vector<LiveInterval*> *newIntervals_;
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const TargetRegisterClass *rc_;
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int stackSlot_;
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const SmallVectorImpl<LiveInterval*> *spillIs_;
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// Values of the current interval that can potentially remat.
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SmallPtrSet<VNInfo*, 8> reMattable_;
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// Values in reMattable_ that failed to remat at some point.
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SmallPtrSet<VNInfo*, 8> usedValues_;
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~InlineSpiller() {}
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public:
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InlineSpiller(MachineFunctionPass &pass,
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MachineFunction &mf,
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VirtRegMap &vrm)
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: pass_(pass),
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mf_(mf),
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lis_(pass.getAnalysis<LiveIntervals>()),
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loops_(pass.getAnalysis<MachineLoopInfo>()),
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vrm_(vrm),
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mfi_(*mf.getFrameInfo()),
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mri_(mf.getRegInfo()),
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tii_(*mf.getTarget().getInstrInfo()),
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tri_(*mf.getTarget().getRegisterInfo()),
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reserved_(tri_.getReservedRegs(mf_)),
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splitAnalysis_(mf, lis_, loops_) {}
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void spill(LiveInterval *li,
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std::vector<LiveInterval*> &newIntervals,
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SmallVectorImpl<LiveInterval*> &spillIs,
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SlotIndex *earliestIndex);
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private:
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bool split();
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bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
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SlotIndex UseIdx);
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bool reMaterializeFor(MachineBasicBlock::iterator MI);
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void reMaterializeAll();
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bool coalesceStackAccess(MachineInstr *MI);
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bool foldMemoryOperand(MachineBasicBlock::iterator MI,
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const SmallVectorImpl<unsigned> &Ops);
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void insertReload(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
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void insertSpill(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
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};
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}
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namespace llvm {
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Spiller *createInlineSpiller(MachineFunctionPass &pass,
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MachineFunction &mf,
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VirtRegMap &vrm) {
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return new InlineSpiller(pass, mf, vrm);
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}
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}
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/// split - try splitting the current interval into pieces that may allocate
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/// separately. Return true if successful.
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bool InlineSpiller::split() {
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// FIXME: Add intra-MBB splitting.
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if (lis_.intervalIsInOneMBB(*li_))
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return false;
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splitAnalysis_.analyze(li_);
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if (const MachineLoop *loop = splitAnalysis_.getBestSplitLoop()) {
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// We can split, but li_ may be left intact with fewer uses.
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if (SplitEditor(splitAnalysis_, lis_, vrm_, *newIntervals_)
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.splitAroundLoop(loop))
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return true;
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}
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return false;
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}
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// OrigIdx are also available with the same value at UseIdx.
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bool InlineSpiller::allUsesAvailableAt(const MachineInstr *OrigMI,
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SlotIndex OrigIdx,
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SlotIndex UseIdx) {
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OrigIdx = OrigIdx.getUseIndex();
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UseIdx = UseIdx.getUseIndex();
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for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = OrigMI->getOperand(i);
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if (!MO.isReg() || !MO.getReg() || MO.getReg() == li_->reg)
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continue;
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// Reserved registers are OK.
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if (MO.isUndef() || !lis_.hasInterval(MO.getReg()))
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continue;
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// We don't want to move any defs.
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if (MO.isDef())
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return false;
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// We cannot depend on virtual registers in spillIs_. They will be spilled.
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for (unsigned si = 0, se = spillIs_->size(); si != se; ++si)
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if ((*spillIs_)[si]->reg == MO.getReg())
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return false;
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LiveInterval &LI = lis_.getInterval(MO.getReg());
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const VNInfo *OVNI = LI.getVNInfoAt(OrigIdx);
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if (!OVNI)
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continue;
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if (OVNI != LI.getVNInfoAt(UseIdx))
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return false;
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}
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return true;
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}
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/// reMaterializeFor - Attempt to rematerialize li_->reg before MI instead of
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/// reloading it.
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bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
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SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
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VNInfo *OrigVNI = li_->getVNInfoAt(UseIdx);
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if (!OrigVNI) {
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DEBUG(dbgs() << "\tadding <undef> flags: ");
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg)
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MO.setIsUndef();
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}
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DEBUG(dbgs() << UseIdx << '\t' << *MI);
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return true;
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}
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if (!reMattable_.count(OrigVNI)) {
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DEBUG(dbgs() << "\tusing non-remat valno " << OrigVNI->id << ": "
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<< UseIdx << '\t' << *MI);
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return false;
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}
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MachineInstr *OrigMI = lis_.getInstructionFromIndex(OrigVNI->def);
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if (!allUsesAvailableAt(OrigMI, OrigVNI->def, UseIdx)) {
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usedValues_.insert(OrigVNI);
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DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
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return false;
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}
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// If the instruction also writes li_->reg, it had better not require the same
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// register for uses and defs.
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bool Reads, Writes;
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SmallVector<unsigned, 8> Ops;
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tie(Reads, Writes) = MI->readsWritesVirtualRegister(li_->reg, &Ops);
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if (Writes) {
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(Ops[i]);
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if (MO.isUse() ? MI->isRegTiedToDefOperand(Ops[i]) : MO.getSubReg()) {
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usedValues_.insert(OrigVNI);
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DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
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return false;
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}
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}
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}
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// Alocate a new register for the remat.
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unsigned NewVReg = mri_.createVirtualRegister(rc_);
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vrm_.grow();
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LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
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NewLI.markNotSpillable();
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newIntervals_->push_back(&NewLI);
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// Finally we can rematerialize OrigMI before MI.
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MachineBasicBlock &MBB = *MI->getParent();
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tii_.reMaterialize(MBB, MI, NewLI.reg, 0, OrigMI, tri_);
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MachineBasicBlock::iterator RematMI = MI;
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SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(--RematMI).getDefIndex();
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DEBUG(dbgs() << "\tremat: " << DefIdx << '\t' << *RematMI);
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// Replace operands
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(Ops[i]);
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if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg) {
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MO.setReg(NewVReg);
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MO.setIsKill();
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}
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}
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DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
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VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, true,
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lis_.getVNInfoAllocator());
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NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
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DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
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return true;
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}
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/// reMaterializeAll - Try to rematerialize as many uses of li_ as possible,
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/// and trim the live ranges after.
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void InlineSpiller::reMaterializeAll() {
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// Do a quick scan of the interval values to find if any are remattable.
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reMattable_.clear();
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usedValues_.clear();
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for (LiveInterval::const_vni_iterator I = li_->vni_begin(),
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E = li_->vni_end(); I != E; ++I) {
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VNInfo *VNI = *I;
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if (VNI->isUnused() || !VNI->isDefAccurate())
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continue;
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MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
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if (!DefMI || !tii_.isTriviallyReMaterializable(DefMI))
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continue;
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reMattable_.insert(VNI);
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}
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// Often, no defs are remattable.
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if (reMattable_.empty())
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return;
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// Try to remat before all uses of li_->reg.
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bool anyRemat = false;
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for (MachineRegisterInfo::use_nodbg_iterator
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RI = mri_.use_nodbg_begin(li_->reg);
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MachineInstr *MI = RI.skipInstruction();)
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anyRemat |= reMaterializeFor(MI);
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if (!anyRemat)
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return;
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// Remove any values that were completely rematted.
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bool anyRemoved = false;
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for (SmallPtrSet<VNInfo*, 8>::iterator I = reMattable_.begin(),
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E = reMattable_.end(); I != E; ++I) {
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VNInfo *VNI = *I;
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if (VNI->hasPHIKill() || usedValues_.count(VNI))
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continue;
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MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
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DEBUG(dbgs() << "\tremoving dead def: " << VNI->def << '\t' << *DefMI);
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lis_.RemoveMachineInstrFromMaps(DefMI);
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vrm_.RemoveMachineInstrFromMaps(DefMI);
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DefMI->eraseFromParent();
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li_->removeValNo(VNI);
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anyRemoved = true;
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}
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if (!anyRemoved)
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return;
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// Removing values may cause debug uses where li_ is not live.
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for (MachineRegisterInfo::use_iterator RI = mri_.use_begin(li_->reg);
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MachineInstr *MI = RI.skipInstruction();) {
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if (!MI->isDebugValue())
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continue;
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// Try to preserve the debug value if li_ is live immediately after it.
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MachineBasicBlock::iterator NextMI = MI;
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++NextMI;
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if (NextMI != MI->getParent()->end() && !lis_.isNotInMIMap(NextMI)) {
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SlotIndex NearIdx = lis_.getInstructionIndex(NextMI);
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if (li_->liveAt(NearIdx))
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continue;
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}
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DEBUG(dbgs() << "Removing debug info due to remat:" << "\t" << *MI);
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MI->eraseFromParent();
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}
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}
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/// If MI is a load or store of stackSlot_, it can be removed.
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bool InlineSpiller::coalesceStackAccess(MachineInstr *MI) {
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int FI = 0;
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unsigned reg;
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if (!(reg = tii_.isLoadFromStackSlot(MI, FI)) &&
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!(reg = tii_.isStoreToStackSlot(MI, FI)))
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return false;
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// We have a stack access. Is it the right register and slot?
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if (reg != li_->reg || FI != stackSlot_)
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return false;
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DEBUG(dbgs() << "Coalescing stack access: " << *MI);
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lis_.RemoveMachineInstrFromMaps(MI);
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MI->eraseFromParent();
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return true;
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}
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/// foldMemoryOperand - Try folding stack slot references in Ops into MI.
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/// Return true on success, and MI will be erased.
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bool InlineSpiller::foldMemoryOperand(MachineBasicBlock::iterator MI,
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const SmallVectorImpl<unsigned> &Ops) {
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// TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
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// operands.
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SmallVector<unsigned, 8> FoldOps;
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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unsigned Idx = Ops[i];
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MachineOperand &MO = MI->getOperand(Idx);
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if (MO.isImplicit())
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continue;
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// FIXME: Teach targets to deal with subregs.
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if (MO.getSubReg())
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return false;
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// Tied use operands should not be passed to foldMemoryOperand.
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if (!MI->isRegTiedToDefOperand(Idx))
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FoldOps.push_back(Idx);
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}
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MachineInstr *FoldMI = tii_.foldMemoryOperand(MI, FoldOps, stackSlot_);
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if (!FoldMI)
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return false;
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lis_.ReplaceMachineInstrInMaps(MI, FoldMI);
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vrm_.addSpillSlotUse(stackSlot_, FoldMI);
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MI->eraseFromParent();
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DEBUG(dbgs() << "\tfolded: " << *FoldMI);
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return true;
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}
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/// insertReload - Insert a reload of NewLI.reg before MI.
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void InlineSpiller::insertReload(LiveInterval &NewLI,
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MachineBasicBlock::iterator MI) {
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MachineBasicBlock &MBB = *MI->getParent();
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SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
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tii_.loadRegFromStackSlot(MBB, MI, NewLI.reg, stackSlot_, rc_, &tri_);
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--MI; // Point to load instruction.
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SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
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vrm_.addSpillSlotUse(stackSlot_, MI);
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DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MI);
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VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, true,
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lis_.getVNInfoAllocator());
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NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
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}
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/// insertSpill - Insert a spill of NewLI.reg after MI.
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void InlineSpiller::insertSpill(LiveInterval &NewLI,
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MachineBasicBlock::iterator MI) {
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MachineBasicBlock &MBB = *MI->getParent();
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SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
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tii_.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, stackSlot_, rc_, &tri_);
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--MI; // Point to store instruction.
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SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
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vrm_.addSpillSlotUse(stackSlot_, MI);
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DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
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VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, true,
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lis_.getVNInfoAllocator());
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NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
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}
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void InlineSpiller::spill(LiveInterval *li,
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std::vector<LiveInterval*> &newIntervals,
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SmallVectorImpl<LiveInterval*> &spillIs,
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SlotIndex *earliestIndex) {
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DEBUG(dbgs() << "Inline spilling " << *li << "\n");
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assert(li->isSpillable() && "Attempting to spill already spilled value.");
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assert(!li->isStackSlot() && "Trying to spill a stack slot.");
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li_ = li;
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newIntervals_ = &newIntervals;
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rc_ = mri_.getRegClass(li->reg);
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spillIs_ = &spillIs;
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if (split())
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return;
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reMaterializeAll();
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// Remat may handle everything.
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if (li_->empty())
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return;
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stackSlot_ = vrm_.getStackSlot(li->reg);
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if (stackSlot_ == VirtRegMap::NO_STACK_SLOT)
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stackSlot_ = vrm_.assignVirt2StackSlot(li->reg);
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// Iterate over instructions using register.
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for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg);
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MachineInstr *MI = RI.skipInstruction();) {
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// Debug values are not allowed to affect codegen.
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if (MI->isDebugValue()) {
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// Modify DBG_VALUE now that the value is in a spill slot.
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uint64_t Offset = MI->getOperand(1).getImm();
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const MDNode *MDPtr = MI->getOperand(2).getMetadata();
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DebugLoc DL = MI->getDebugLoc();
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if (MachineInstr *NewDV = tii_.emitFrameIndexDebugValue(mf_, stackSlot_,
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Offset, MDPtr, DL)) {
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DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
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MachineBasicBlock *MBB = MI->getParent();
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MBB->insert(MBB->erase(MI), NewDV);
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} else {
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DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
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MI->eraseFromParent();
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}
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continue;
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}
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// Stack slot accesses may coalesce away.
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if (coalesceStackAccess(MI))
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continue;
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// Analyze instruction.
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bool Reads, Writes;
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SmallVector<unsigned, 8> Ops;
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tie(Reads, Writes) = MI->readsWritesVirtualRegister(li->reg, &Ops);
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// Attempt to fold memory ops.
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if (foldMemoryOperand(MI, Ops))
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continue;
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// Allocate interval around instruction.
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// FIXME: Infer regclass from instruction alone.
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unsigned NewVReg = mri_.createVirtualRegister(rc_);
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vrm_.grow();
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LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
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NewLI.markNotSpillable();
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if (Reads)
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insertReload(NewLI, MI);
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// Rewrite instruction operands.
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bool hasLiveDef = false;
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(Ops[i]);
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MO.setReg(NewVReg);
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if (MO.isUse()) {
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if (!MI->isRegTiedToDefOperand(Ops[i]))
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MO.setIsKill();
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} else {
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if (!MO.isDead())
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hasLiveDef = true;
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}
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}
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// FIXME: Use a second vreg if instruction has no tied ops.
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if (Writes && hasLiveDef)
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insertSpill(NewLI, MI);
|
|
|
|
DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
|
|
newIntervals.push_back(&NewLI);
|
|
}
|
|
}
|