mirror of
https://github.com/c64scene-ar/llvm-6502.git
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1ee2925742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
419 lines
13 KiB
C++
419 lines
13 KiB
C++
//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the "Instituto Nokia de Tecnologia" and
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// is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMInstrInfo.h"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMGenInstrInfo.inc"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
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cl::desc("Enable ARM 2-addr to 3-addr conv"));
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ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
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: TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])),
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RI(*this, STI) {
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}
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const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
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return &ARM::GPRRegClass;
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg) const {
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MachineOpCode oc = MI.getOpcode();
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switch (oc) {
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default:
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return false;
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case ARM::FCPYS:
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case ARM::FCPYD:
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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case ARM::MOVrr:
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case ARM::tMOVrr:
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assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"Invalid ARM MOV instruction");
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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}
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}
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unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
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switch (MI->getOpcode()) {
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default: break;
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case ARM::LDR:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isReg() &&
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MI->getOperand(3).isImmediate() &&
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MI->getOperand(2).getReg() == 0 &&
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MI->getOperand(3).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(1).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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case ARM::FLDD:
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case ARM::FLDS:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isImmediate() &&
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MI->getOperand(2).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(1).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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case ARM::tLDRspi:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isImmediate() &&
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MI->getOperand(2).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(1).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case ARM::STR:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isReg() &&
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MI->getOperand(3).isImmediate() &&
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MI->getOperand(2).getReg() == 0 &&
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MI->getOperand(3).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(1).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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case ARM::FSTD:
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case ARM::FSTS:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isImmediate() &&
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MI->getOperand(2).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(1).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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case ARM::tSTRspi:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isImmediate() &&
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MI->getOperand(2).getImmedValue() == 0) {
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FrameIndex = MI->getOperand(1).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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static unsigned getUnindexedOpcode(unsigned Opc) {
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switch (Opc) {
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default: break;
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case ARM::LDR_PRE:
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case ARM::LDR_POST:
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return ARM::LDR;
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case ARM::LDRH_PRE:
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case ARM::LDRH_POST:
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return ARM::LDRH;
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case ARM::LDRB_PRE:
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case ARM::LDRB_POST:
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return ARM::LDRB;
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case ARM::LDRSH_PRE:
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case ARM::LDRSH_POST:
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return ARM::LDRSH;
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case ARM::LDRSB_PRE:
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case ARM::LDRSB_POST:
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return ARM::LDRSB;
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case ARM::STR_PRE:
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case ARM::STR_POST:
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return ARM::STR;
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case ARM::STRH_PRE:
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case ARM::STRH_POST:
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return ARM::STRH;
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case ARM::STRB_PRE:
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case ARM::STRB_POST:
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return ARM::STRB;
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}
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return 0;
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}
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MachineInstr *
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ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables &LV) const {
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if (!EnableARM3Addr)
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return NULL;
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MachineInstr *MI = MBBI;
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unsigned TSFlags = MI->getInstrDescriptor()->TSFlags;
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bool isPre = false;
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switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
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default: return NULL;
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case ARMII::IndexModePre:
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isPre = true;
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break;
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case ARMII::IndexModePost:
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break;
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}
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// Try spliting an indexed load / store to a un-indexed one plus an add/sub
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// operation.
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unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
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if (MemOpc == 0)
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return NULL;
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MachineInstr *UpdateMI = NULL;
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MachineInstr *MemMI = NULL;
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unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
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unsigned NumOps = MI->getNumOperands();
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bool isLoad = (MI->getInstrDescriptor()->Flags & M_LOAD_FLAG) != 0;
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const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
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const MachineOperand &Base = MI->getOperand(2);
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const MachineOperand &Offset = MI->getOperand(NumOps-2);
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unsigned WBReg = WB.getReg();
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unsigned BaseReg = Base.getReg();
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unsigned OffReg = Offset.getReg();
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unsigned OffImm = MI->getOperand(NumOps-1).getImm();
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switch (AddrMode) {
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default:
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assert(false && "Unknown indexed op!");
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return NULL;
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case ARMII::AddrMode2: {
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bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
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unsigned Amt = ARM_AM::getAM2Offset(OffImm);
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if (OffReg == 0) {
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int SOImmVal = ARM_AM::getSOImmVal(Amt);
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if (SOImmVal == -1)
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// Can't encode it in a so_imm operand. This transformation will
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// add more than 1 instruction. Abandon!
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return NULL;
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UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
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.addReg(BaseReg).addImm(SOImmVal);
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} else if (Amt != 0) {
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ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
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unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
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UpdateMI = BuildMI(get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
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.addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc);
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} else
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UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
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.addReg(BaseReg).addReg(OffReg);
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break;
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}
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case ARMII::AddrMode3 : {
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bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
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unsigned Amt = ARM_AM::getAM3Offset(OffImm);
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if (OffReg == 0)
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// Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
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UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
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.addReg(BaseReg).addImm(Amt);
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else
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UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
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.addReg(BaseReg).addReg(OffReg);
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break;
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}
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}
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std::vector<MachineInstr*> NewMIs;
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if (isPre) {
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if (isLoad)
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MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
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.addReg(WBReg).addReg(0).addImm(0);
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else
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MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
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.addReg(WBReg).addReg(0).addImm(0);
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NewMIs.push_back(MemMI);
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NewMIs.push_back(UpdateMI);
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} else {
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if (isLoad)
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MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
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.addReg(BaseReg).addReg(0).addImm(0);
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else
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MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
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.addReg(BaseReg).addReg(0).addImm(0);
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if (WB.isDead())
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UpdateMI->getOperand(0).setIsDead();
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NewMIs.push_back(UpdateMI);
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NewMIs.push_back(MemMI);
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}
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// Transfer LiveVariables states, kill / dead info.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.getReg() &&
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MRegisterInfo::isVirtualRegister(MO.getReg())) {
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unsigned Reg = MO.getReg();
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LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
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if (MO.isDef()) {
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MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
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if (MO.isDead())
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LV.addVirtualRegisterDead(Reg, NewMI);
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// Update the defining instruction.
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if (VI.DefInst == MI)
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VI.DefInst = NewMI;
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}
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if (MO.isUse() && MO.isKill()) {
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for (unsigned j = 0; j < 2; ++j) {
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// Look at the two new MI's in reverse order.
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MachineInstr *NewMI = NewMIs[j];
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MachineOperand *NMO = NewMI->findRegisterUseOperand(Reg);
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if (!NMO)
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continue;
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LV.addVirtualRegisterKilled(Reg, NewMI);
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if (VI.removeKill(MI))
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VI.Kills.push_back(NewMI);
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break;
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}
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}
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}
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}
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MFI->insert(MBBI, NewMIs[1]);
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MFI->insert(MBBI, NewMIs[0]);
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return NewMIs[0];
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}
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// Branch analysis.
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bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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std::vector<MachineOperand> &Cond) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode()))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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unsigned LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
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if (LastOpc == ARM::B || LastOpc == ARM::tB) {
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TBB = LastInst->getOperand(0).getMachineBasicBlock();
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return false;
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}
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if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(0).getMachineBasicBlock();
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Cond.push_back(LastInst->getOperand(1));
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return false;
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}
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return true; // Can't handle indirect branch.
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}
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// Get the instruction before it if it is a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() &&
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isTerminatorInstr((--I)->getOpcode()))
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return true;
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// If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
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(SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
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TBB = SecondLastInst->getOperand(0).getMachineBasicBlock();
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Cond.push_back(SecondLastInst->getOperand(1));
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FBB = LastInst->getOperand(0).getMachineBasicBlock();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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void ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
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int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return;
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--I;
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if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
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return;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return;
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--I;
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if (I->getOpcode() != BccOpc)
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return;
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// Remove the branch.
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I->eraseFromParent();
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}
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void ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const std::vector<MachineOperand> &Cond) const {
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
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int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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"ARM branch conditions have two components!");
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if (FBB == 0) {
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if (Cond.empty()) // Unconditional branch?
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BuildMI(&MBB, get(BOpc)).addMBB(TBB);
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else
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BuildMI(&MBB, get(BccOpc)).addMBB(TBB).addImm(Cond[0].getImm());
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return;
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}
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// Two-way conditional branch.
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BuildMI(&MBB, get(BccOpc)).addMBB(TBB).addImm(Cond[0].getImm());
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BuildMI(&MBB, get(BOpc)).addMBB(FBB);
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}
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bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
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if (MBB.empty()) return false;
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switch (MBB.back().getOpcode()) {
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case ARM::B:
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case ARM::tB: // Uncond branch.
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case ARM::BR_JTr: // Jumptable branch.
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case ARM::BR_JTm: // Jumptable branch through mem.
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case ARM::BR_JTadd: // Jumptable branch add to pc.
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return true;
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default: return false;
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}
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}
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bool ARMInstrInfo::
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ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
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ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
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Cond[0].setImm(ARMCC::getOppositeCondition(CC));
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return false;
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}
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