mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Make LABEL a builtin opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
2b935d55b0
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1ee2925742
@ -266,6 +266,10 @@ namespace llvm {
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/// instruction that is an inline asm.
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void printInlineAsm(const MachineInstr *MI) const;
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/// printLabel - This method prints a local label used by debug and
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/// exception handling tables.
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void printLabel(const MachineInstr *MI) const;
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/// printBasicBlockLabel - This method prints the label for the specified
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/// MachineBasicBlock
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virtual void printBasicBlockLabel(const MachineBasicBlock *MBB,
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@ -436,6 +436,13 @@ namespace ISD {
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// Operand #2n+3: A TargetConstant, indicating if the reg is a use/def
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// Operand #last: Optional, an incoming flag.
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INLINEASM,
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// LABEL - Represents a label in mid basic block used to track
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// locations needed for debug and exception handling tables. This node
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// returns a chain.
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// Operand #0 : input chain.
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// Operand #1 : module unique number use to identify the label.
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LABEL,
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// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
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// value, the same type as the pointer type for the system, and an output
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@ -503,12 +510,6 @@ namespace ISD {
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// produces a token chain as output.
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DEBUG_LOC,
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// DEBUG_LABEL - This node is used to mark a location in the code where a
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// label should be generated for use by the debug information. It takes a
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// token chain as input and then a unique id (provided by MachineDebugInfo.)
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// It produces a token chain as output.
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DEBUG_LABEL,
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// BUILTIN_OP_END - This must be the last enum value in this list.
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BUILTIN_OP_END
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};
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@ -166,7 +166,8 @@ public:
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// Invariant opcodes: All instruction sets have these as their low opcodes.
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enum {
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PHI = 0,
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INLINEASM = 1
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INLINEASM = 1,
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LABEL = 2
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};
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unsigned getNumOpcodes() const { return NumOpcodes; }
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@ -263,13 +264,6 @@ public:
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return get(Opcode).getOperandConstraint(OpNum, Constraint);
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}
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/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
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/// instruction if it has one. This is used by codegen passes that update
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/// DWARF line number info as they modify the code.
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virtual unsigned getDWARF_LABELOpcode() const {
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return 0;
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}
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/// Return true if the instruction is a register to register move
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/// and leave the source and dest operands in the passed parameters.
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virtual bool isMoveInstr(const MachineInstr& MI,
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@ -1029,6 +1029,16 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const {
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O << "\n\t" << TAI->getInlineAsmEnd() << "\n";
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}
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/// printLabel - This method prints a local label used by debug and
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/// exception handling tables.
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void AsmPrinter::printLabel(const MachineInstr *MI) const {
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if (AsmVerbose) O << "\n";
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O << TAI->getPrivateGlobalPrefix()
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<< "debug_loc"
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<< MI->getOperand(0).getImmedValue()
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<< ":\n";
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}
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/// PrintAsmOperand - Print the specified operand of MI, an INLINEASM
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/// instruction, using the specified assembler variant. Targets should
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/// overried this to format as appropriate.
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@ -74,16 +74,12 @@ void BranchFolder::RemoveDeadBlock(MachineBasicBlock *MBB) {
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while (!MBB->succ_empty())
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MBB->removeSuccessor(MBB->succ_end()-1);
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// If there is DWARF info to active, check to see if there are any DWARF_LABEL
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// If there is DWARF info to active, check to see if there are any LABEL
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// records in the basic block. If so, unregister them from MachineDebugInfo.
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if (MDI && !MBB->empty()) {
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unsigned DWARF_LABELOpc = TII->getDWARF_LABELOpcode();
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assert(DWARF_LABELOpc &&
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"Target supports dwarf but didn't implement getDWARF_LABELOpcode!");
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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if ((unsigned)I->getOpcode() == DWARF_LABELOpc) {
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if ((unsigned)I->getOpcode() == TargetInstrInfo::LABEL) {
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// The label ID # is always operand #0, an immediate.
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MDI->InvalidateLabel(I->getOperand(0).getImm());
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}
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@ -1649,9 +1649,6 @@ bool DebugLabelFolder::runOnMachineFunction(MachineFunction &MF) {
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// Get target instruction info.
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const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
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if (!TII) return false;
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// Get target version of the debug label opcode.
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unsigned DWARF_LABELOpc = TII->getDWARF_LABELOpcode();
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if (!DWARF_LABELOpc) return false;
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// Track if change is made.
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bool MadeChange = false;
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@ -1664,7 +1661,7 @@ bool DebugLabelFolder::runOnMachineFunction(MachineFunction &MF) {
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// Iterate through instructions.
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for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ) {
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// Is it a debug label.
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if ((unsigned)I->getOpcode() == DWARF_LABELOpc) {
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if ((unsigned)I->getOpcode() == TargetInstrInfo::LABEL) {
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// The label ID # is always operand #0, an immediate.
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unsigned NextLabel = I->getOperand(0).getImm();
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@ -737,9 +737,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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case TargetLowering::Expand: {
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MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
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bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
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bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
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bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
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if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
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if (DebugInfo && (useDEBUG_LOC || useLABEL)) {
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const std::string &FName =
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cast<StringSDNode>(Node->getOperand(3))->getValue();
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const std::string &DirName =
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@ -761,7 +761,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
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unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
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Ops.push_back(DAG.getConstant(ID, MVT::i32));
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Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
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Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
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}
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} else {
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Result = Tmp1; // chain
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@ -803,9 +803,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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}
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break;
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case ISD::DEBUG_LABEL:
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assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
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switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
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case ISD::LABEL:
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assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
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switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Legal:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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@ -452,6 +452,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
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assert(0 && "This target-independent node should have been selected!");
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case ISD::EntryToken: // fall thru
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case ISD::TokenFactor:
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case ISD::LABEL:
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break;
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case ISD::CopyToReg: {
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unsigned InReg;
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@ -2691,6 +2691,7 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
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case ISD::UNDEF: return "undef";
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case ISD::MERGE_VALUES: return "mergevalues";
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case ISD::INLINEASM: return "inlineasm";
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case ISD::LABEL: return "label";
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case ISD::HANDLENODE: return "handlenode";
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case ISD::FORMAL_ARGUMENTS: return "formal_arguments";
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case ISD::CALL: return "call";
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@ -2811,7 +2812,6 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
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// Debug info
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case ISD::LOCATION: return "location";
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case ISD::DEBUG_LOC: return "debug_loc";
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case ISD::DEBUG_LABEL: return "debug_label";
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case ISD::CONDCODE:
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switch (cast<CondCodeSDNode>(this)->get()) {
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@ -1980,7 +1980,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
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if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
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unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
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DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
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DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
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DAG.getConstant(LabelID, MVT::i32)));
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}
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@ -1991,7 +1991,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
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if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
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unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
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DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
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DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
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getRoot(), DAG.getConstant(LabelID, MVT::i32)));
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}
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@ -2003,7 +2003,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
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if (DebugInfo && FSI.getSubprogram() &&
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DebugInfo->Verify(FSI.getSubprogram())) {
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unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
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DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
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DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
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getRoot(), DAG.getConstant(LabelID, MVT::i32)));
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}
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@ -336,6 +336,8 @@ unsigned ARMConstantIslands::GetInstSize(MachineInstr *MI) const {
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// If this machine instr is an inline asm, measure it.
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if (MI->getOpcode() == ARM::INLINEASM)
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return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
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if (MI->getOpcode() == ARM::LABEL)
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return 0;
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assert(0 && "Unknown or unset size field for instr!");
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break;
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case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
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@ -147,7 +147,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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// FIXME - use subtarget debug flags
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if (Subtarget->isTargetDarwin())
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setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
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setOperationAction(ISD::LABEL, MVT::Other, Expand);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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@ -30,10 +30,6 @@ ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
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RI(*this, STI) {
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}
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unsigned ARMInstrInfo::getDWARF_LABELOpcode() const {
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return ARM::DWARF_LABEL;
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}
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const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
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return &ARM::GPRRegClass;
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}
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@ -80,11 +80,6 @@ public:
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *getPointerRegClass() const;
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/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
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/// instruction if it has one. This is used by codegen passes that update
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/// DWARF line number info as they modify the code.
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virtual unsigned getDWARF_LABELOpcode() const;
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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@ -513,11 +513,6 @@ PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file),
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".loc $file, $line, $col",
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[(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
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def DWARF_LABEL :
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PseudoInst<(ops i32imm:$id),
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"\nLdebug_loc${id:no_hash}:",
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[(dwarf_label (i32 imm:$id))]>;
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def PICADD : AI1<(ops GPR:$dst, GPR:$a, pclabel:$cp),
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"\n$cp:\n\tadd $dst, pc, $a",
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[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
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@ -109,7 +109,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
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setOperationAction(ISD::LABEL, MVT::Other, Expand);
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// Not implemented yet.
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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@ -88,7 +88,7 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
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setOperationAction(ISD::LABEL, MVT::Other, Expand);
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//IA64 has these, but they are not implemented
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setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
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@ -66,6 +66,9 @@ static unsigned getNumBytesForInstruction(MachineInstr *MI) {
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const char *AsmStr = MI->getOperand(0).getSymbolName();
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return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
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}
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case PPC::LABEL: {
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return 0;
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}
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default:
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return 4; // PowerPC instructions are all 4 bytes
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}
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@ -147,7 +147,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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// FIXME - use subtarget debug flags
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if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
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setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
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setOperationAction(ISD::LABEL, MVT::Other, Expand);
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// We want to legalize GlobalAddress and ConstantPool nodes into the
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// appropriate instructions to materialize the address.
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@ -77,13 +77,6 @@ public:
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/// This is used for addressing modes.
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virtual const TargetRegisterClass *getPointerRegClass() const;
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/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
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/// instruction if it has one. This is used by codegen passes that update
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/// DWARF line number info as they modify the code.
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virtual unsigned getDWARF_LABELOpcode() const {
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return PPC::DWARF_LABEL;
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}
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// Return true if the instruction is a register to register move and
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// leave the source and dest operands in the passed parameters.
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//
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@ -1015,10 +1015,6 @@ def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
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[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
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(i32 imm:$file))]>;
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def DWARF_LABEL : Pseudo<(ops i32imm:$id),
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"\n${:private}debug_loc$id:",
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[(dwarf_label (i32 imm:$id))]>;
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Patterns
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//
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@ -822,7 +822,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
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if (hasInfo) {
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// Mark effective beginning of when frame pointer becomes valid.
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FrameLabelId = DebugInfo->NextLabelID();
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BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(FrameLabelId);
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BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
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}
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// Adjust stack pointer: r1 += NegFrameSize.
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@ -902,7 +902,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
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// Mark effective beginning of when frame pointer is ready.
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unsigned ReadyLabelId = DebugInfo->NextLabelID();
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BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(ReadyLabelId);
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BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
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MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
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(IsPPC64 ? PPC::X1 : PPC::R1));
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@ -207,7 +207,7 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
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setOperationAction(ISD::LABEL, MVT::Other, Expand);
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// RET must be custom lowered, to meet ABI requirements
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setOperationAction(ISD::RET , MVT::Other, Custom);
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@ -266,6 +266,12 @@ def INLINEASM : Instruction {
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let AsmString = "";
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let Namespace = "TargetInstrInfo";
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}
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def LABEL : Instruction {
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let OperandList = (ops i32imm:$id);
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let AsmString = "";
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let Namespace = "TargetInstrInfo";
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let hasCtrlDep = 1;
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}
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//===----------------------------------------------------------------------===//
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// AsmWriter - This class can be implemented by targets that need to customize
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@ -755,8 +755,5 @@ def SDT_dwarf_loc : SDTypeProfile<0, 3,
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[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
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def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
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def SDT_dwarf_label : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def dwarf_label : SDNode<"ISD::DEBUG_LABEL", SDT_dwarf_label,[SDNPHasChain]>;
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@ -630,6 +630,8 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
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assert(0 && "psuedo instructions should be removed before code emission");
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case TargetInstrInfo::INLINEASM:
|
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assert(0 && "JIT does not support inline asm!\n");
|
||||
case TargetInstrInfo::LABEL:
|
||||
assert(0 && "JIT does not support meta labels!\n");
|
||||
case X86::IMPLICIT_USE:
|
||||
case X86::IMPLICIT_DEF:
|
||||
case X86::IMPLICIT_DEF_GR8:
|
||||
|
@ -235,7 +235,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
|
||||
if (!Subtarget->isTargetDarwin() &&
|
||||
!Subtarget->isTargetELF() &&
|
||||
!Subtarget->isTargetCygMing())
|
||||
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
|
||||
setOperationAction(ISD::LABEL, MVT::Other, Expand);
|
||||
|
||||
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
|
||||
setOperationAction(ISD::VASTART , MVT::Other, Custom);
|
||||
|
@ -26,14 +26,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
||||
TM(tm), RI(tm, *this) {
|
||||
}
|
||||
|
||||
/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
|
||||
/// instruction if it has one. This is used by codegen passes that update
|
||||
/// DWARF line number info as they modify the code.
|
||||
unsigned X86InstrInfo::getDWARF_LABELOpcode() const {
|
||||
return X86::DWARF_LABEL;
|
||||
}
|
||||
|
||||
|
||||
bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
|
||||
unsigned& sourceReg,
|
||||
unsigned& destReg) const {
|
||||
|
@ -237,11 +237,6 @@ public:
|
||||
unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
|
||||
unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
|
||||
|
||||
/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
|
||||
/// instruction if it has one. This is used by codegen passes that update
|
||||
/// DWARF line number info as they modify the code.
|
||||
virtual unsigned getDWARF_LABELOpcode() const;
|
||||
|
||||
/// convertToThreeAddress - This method must be implemented by targets that
|
||||
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
|
||||
/// may be able to convert a two-address instruction into a true
|
||||
|
@ -2449,10 +2449,6 @@ def DWARF_LOC : I<0, Pseudo, (ops i32imm:$line, i32imm:$col, i32imm:$file),
|
||||
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
|
||||
(i32 imm:$file))]>;
|
||||
|
||||
def DWARF_LABEL : I<0, Pseudo, (ops i32imm:$id),
|
||||
"\n${:private}debug_loc${id:debug}:",
|
||||
[(dwarf_label (i32 imm:$id))]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Non-Instruction Patterns
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
@ -1026,7 +1026,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
if (hasInfo) {
|
||||
// Mark effective beginning of when frame pointer becomes valid.
|
||||
FrameLabelId = DebugInfo->NextLabelID();
|
||||
BuildMI(MBB, MBBI, TII.get(X86::DWARF_LABEL)).addImm(FrameLabelId);
|
||||
BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
|
||||
}
|
||||
|
||||
if (hasFP(MF)) {
|
||||
@ -1078,7 +1078,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
|
||||
// Mark effective beginning of when frame pointer is ready.
|
||||
unsigned ReadyLabelId = DebugInfo->NextLabelID();
|
||||
BuildMI(MBB, MBBI, TII.get(X86::DWARF_LABEL)).addImm(ReadyLabelId);
|
||||
BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
|
||||
|
||||
MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
|
||||
MachineLocation FPSrc(MachineLocation::VirtualFP);
|
||||
|
Loading…
Reference in New Issue
Block a user