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Make LABEL a builtin opcode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey 2007-01-26 14:34:52 +00:00
parent 2b935d55b0
commit 1ee2925742
31 changed files with 60 additions and 89 deletions
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4
include/llvm/CodeGen/AsmPrinter.h
View File

@ -266,6 +266,10 @@ namespace llvm {
/// instruction that is an inline asm.
void printInlineAsm(const MachineInstr *MI) const;
/// printLabel - This method prints a local label used by debug and
/// exception handling tables.
void printLabel(const MachineInstr *MI) const;
/// printBasicBlockLabel - This method prints the label for the specified
/// MachineBasicBlock
virtual void printBasicBlockLabel(const MachineBasicBlock *MBB,

13
include/llvm/CodeGen/SelectionDAGNodes.h
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@ -436,6 +436,13 @@ namespace ISD {
// Operand #2n+3: A TargetConstant, indicating if the reg is a use/def
// Operand #last: Optional, an incoming flag.
INLINEASM,
// LABEL - Represents a label in mid basic block used to track
// locations needed for debug and exception handling tables. This node
// returns a chain.
// Operand #0 : input chain.
// Operand #1 : module unique number use to identify the label.
LABEL,
// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
// value, the same type as the pointer type for the system, and an output
@ -503,12 +510,6 @@ namespace ISD {
// produces a token chain as output.
DEBUG_LOC,
// DEBUG_LABEL - This node is used to mark a location in the code where a
// label should be generated for use by the debug information. It takes a
// token chain as input and then a unique id (provided by MachineDebugInfo.)
// It produces a token chain as output.
DEBUG_LABEL,
// BUILTIN_OP_END - This must be the last enum value in this list.
BUILTIN_OP_END
};

10
include/llvm/Target/TargetInstrInfo.h
View File

@ -166,7 +166,8 @@ public:
// Invariant opcodes: All instruction sets have these as their low opcodes.
enum {
PHI = 0,
INLINEASM = 1
INLINEASM = 1,
LABEL = 2
};
unsigned getNumOpcodes() const { return NumOpcodes; }
@ -263,13 +264,6 @@ public:
return get(Opcode).getOperandConstraint(OpNum, Constraint);
}
/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
/// instruction if it has one. This is used by codegen passes that update
/// DWARF line number info as they modify the code.
virtual unsigned getDWARF_LABELOpcode() const {
return 0;
}
/// Return true if the instruction is a register to register move
/// and leave the source and dest operands in the passed parameters.
virtual bool isMoveInstr(const MachineInstr& MI,

10
lib/CodeGen/AsmPrinter.cpp
View File

@ -1029,6 +1029,16 @@ void AsmPrinter::printInlineAsm(const MachineInstr *MI) const {
O << "\n\t" << TAI->getInlineAsmEnd() << "\n";
}
/// printLabel - This method prints a local label used by debug and
/// exception handling tables.
void AsmPrinter::printLabel(const MachineInstr *MI) const {
if (AsmVerbose) O << "\n";
O << TAI->getPrivateGlobalPrefix()
<< "debug_loc"
<< MI->getOperand(0).getImmedValue()
<< ":\n";
}
/// PrintAsmOperand - Print the specified operand of MI, an INLINEASM
/// instruction, using the specified assembler variant. Targets should
/// overried this to format as appropriate.

8
lib/CodeGen/BranchFolding.cpp
View File

@ -74,16 +74,12 @@ void BranchFolder::RemoveDeadBlock(MachineBasicBlock *MBB) {
while (!MBB->succ_empty())
MBB->removeSuccessor(MBB->succ_end()-1);
// If there is DWARF info to active, check to see if there are any DWARF_LABEL
// If there is DWARF info to active, check to see if there are any LABEL
// records in the basic block. If so, unregister them from MachineDebugInfo.
if (MDI && !MBB->empty()) {
unsigned DWARF_LABELOpc = TII->getDWARF_LABELOpcode();
assert(DWARF_LABELOpc &&
"Target supports dwarf but didn't implement getDWARF_LABELOpcode!");
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
if ((unsigned)I->getOpcode() == DWARF_LABELOpc) {
if ((unsigned)I->getOpcode() == TargetInstrInfo::LABEL) {
// The label ID # is always operand #0, an immediate.
MDI->InvalidateLabel(I->getOperand(0).getImm());
}

5
lib/CodeGen/MachineDebugInfo.cpp
View File

@ -1649,9 +1649,6 @@ bool DebugLabelFolder::runOnMachineFunction(MachineFunction &MF) {
// Get target instruction info.
const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
if (!TII) return false;
// Get target version of the debug label opcode.
unsigned DWARF_LABELOpc = TII->getDWARF_LABELOpcode();
if (!DWARF_LABELOpc) return false;
// Track if change is made.
bool MadeChange = false;
@ -1664,7 +1661,7 @@ bool DebugLabelFolder::runOnMachineFunction(MachineFunction &MF) {
// Iterate through instructions.
for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ) {
// Is it a debug label.
if ((unsigned)I->getOpcode() == DWARF_LABELOpc) {
if ((unsigned)I->getOpcode() == TargetInstrInfo::LABEL) {
// The label ID # is always operand #0, an immediate.
unsigned NextLabel = I->getOperand(0).getImm();

12
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -737,9 +737,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
case TargetLowering::Expand: {
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
if (DebugInfo && (useDEBUG_LOC || useLABEL)) {
const std::string &FName =
cast<StringSDNode>(Node->getOperand(3))->getValue();
const std::string &DirName =
@ -761,7 +761,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
Ops.push_back(DAG.getConstant(ID, MVT::i32));
Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
}
} else {
Result = Tmp1; // chain
@ -803,9 +803,9 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
}
break;
case ISD::DEBUG_LABEL:
assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
case ISD::LABEL:
assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.

1
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -452,6 +452,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
assert(0 && "This target-independent node should have been selected!");
case ISD::EntryToken: // fall thru
case ISD::TokenFactor:
case ISD::LABEL:
break;
case ISD::CopyToReg: {
unsigned InReg;

2
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2691,6 +2691,7 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::UNDEF: return "undef";
case ISD::MERGE_VALUES: return "mergevalues";
case ISD::INLINEASM: return "inlineasm";
case ISD::LABEL: return "label";
case ISD::HANDLENODE: return "handlenode";
case ISD::FORMAL_ARGUMENTS: return "formal_arguments";
case ISD::CALL: return "call";
@ -2811,7 +2812,6 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
// Debug info
case ISD::LOCATION: return "location";
case ISD::DEBUG_LOC: return "debug_loc";
case ISD::DEBUG_LABEL: return "debug_label";
case ISD::CONDCODE:
switch (cast<CondCodeSDNode>(this)->get()) {

6
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1980,7 +1980,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
DAG.getConstant(LabelID, MVT::i32)));
}
@ -1991,7 +1991,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
getRoot(), DAG.getConstant(LabelID, MVT::i32)));
}
@ -2003,7 +2003,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
if (DebugInfo && FSI.getSubprogram() &&
DebugInfo->Verify(FSI.getSubprogram())) {
unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other,
getRoot(), DAG.getConstant(LabelID, MVT::i32)));
}

2
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -336,6 +336,8 @@ unsigned ARMConstantIslands::GetInstSize(MachineInstr *MI) const {
// If this machine instr is an inline asm, measure it.
if (MI->getOpcode() == ARM::INLINEASM)
return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
if (MI->getOpcode() == ARM::LABEL)
return 0;
assert(0 && "Unknown or unset size field for instr!");
break;
case ARMII::Size8Bytes: return 8; // Arm instruction x 2.

2
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -147,7 +147,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// FIXME - use subtarget debug flags
if (Subtarget->isTargetDarwin())
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::LABEL, MVT::Other, Expand);
setOperationAction(ISD::RET, MVT::Other, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);

4
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -30,10 +30,6 @@ ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
RI(*this, STI) {
}
unsigned ARMInstrInfo::getDWARF_LABELOpcode() const {
return ARM::DWARF_LABEL;
}
const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
return &ARM::GPRRegClass;
}

5
lib/Target/ARM/ARMInstrInfo.h
View File

@ -80,11 +80,6 @@ public:
/// This is used for addressing modes.
virtual const TargetRegisterClass *getPointerRegClass() const;
/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
/// instruction if it has one. This is used by codegen passes that update
/// DWARF line number info as they modify the code.
virtual unsigned getDWARF_LABELOpcode() const;
/// Return true if the instruction is a register to register move and
/// leave the source and dest operands in the passed parameters.
///

5
lib/Target/ARM/ARMInstrInfo.td
View File

@ -513,11 +513,6 @@ PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file),
".loc $file, $line, $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
def DWARF_LABEL :
PseudoInst<(ops i32imm:$id),
"\nLdebug_loc${id:no_hash}:",
[(dwarf_label (i32 imm:$id))]>;
def PICADD : AI1<(ops GPR:$dst, GPR:$a, pclabel:$cp),
"\n$cp:\n\tadd $dst, pc, $a",
[(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;

2
lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -109,7 +109,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::LABEL, MVT::Other, Expand);
// Not implemented yet.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);

2
lib/Target/IA64/IA64ISelLowering.cpp
View File

@ -88,7 +88,7 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::LABEL, MVT::Other, Expand);
//IA64 has these, but they are not implemented
setOperationAction(ISD::CTTZ , MVT::i64 , Expand);

3
lib/Target/PowerPC/PPCBranchSelector.cpp
View File

@ -66,6 +66,9 @@ static unsigned getNumBytesForInstruction(MachineInstr *MI) {
const char *AsmStr = MI->getOperand(0).getSymbolName();
return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
}
case PPC::LABEL: {
return 0;
}
default:
return 4; // PowerPC instructions are all 4 bytes
}

2
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -147,7 +147,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// FIXME - use subtarget debug flags
if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::LABEL, MVT::Other, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.

7
lib/Target/PowerPC/PPCInstrInfo.h
View File

@ -77,13 +77,6 @@ public:
/// This is used for addressing modes.
virtual const TargetRegisterClass *getPointerRegClass() const;
/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
/// instruction if it has one. This is used by codegen passes that update
/// DWARF line number info as they modify the code.
virtual unsigned getDWARF_LABELOpcode() const {
return PPC::DWARF_LABEL;
}
// Return true if the instruction is a register to register move and
// leave the source and dest operands in the passed parameters.
//

4
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -1015,10 +1015,6 @@ def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
(i32 imm:$file))]>;
def DWARF_LABEL : Pseudo<(ops i32imm:$id),
"\n${:private}debug_loc$id:",
[(dwarf_label (i32 imm:$id))]>;
//===----------------------------------------------------------------------===//
// PowerPC Instruction Patterns
//

4
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -822,7 +822,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
if (hasInfo) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = DebugInfo->NextLabelID();
BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(FrameLabelId);
BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId);
}
// Adjust stack pointer: r1 += NegFrameSize.
@ -902,7 +902,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = DebugInfo->NextLabelID();
BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(ReadyLabelId);
BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId);
MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
(IsPPC64 ? PPC::X1 : PPC::R1));

2
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -207,7 +207,7 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::LABEL, MVT::Other, Expand);
// RET must be custom lowered, to meet ABI requirements
setOperationAction(ISD::RET , MVT::Other, Custom);

6
lib/Target/Target.td
View File

@ -266,6 +266,12 @@ def INLINEASM : Instruction {
let AsmString = "";
let Namespace = "TargetInstrInfo";
}
def LABEL : Instruction {
let OperandList = (ops i32imm:$id);
let AsmString = "";
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
}
//===----------------------------------------------------------------------===//
// AsmWriter - This class can be implemented by targets that need to customize

3
lib/Target/TargetSelectionDAG.td
View File

@ -755,8 +755,5 @@ def SDT_dwarf_loc : SDTypeProfile<0, 3,
[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
def SDT_dwarf_label : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
def dwarf_label : SDNode<"ISD::DEBUG_LABEL", SDT_dwarf_label,[SDNPHasChain]>;

2
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -630,6 +630,8 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
assert(0 && "psuedo instructions should be removed before code emission");
case TargetInstrInfo::INLINEASM:
assert(0 && "JIT does not support inline asm!\n");
case TargetInstrInfo::LABEL:
assert(0 && "JIT does not support meta labels!\n");
case X86::IMPLICIT_USE:
case X86::IMPLICIT_DEF:
case X86::IMPLICIT_DEF_GR8:

2
lib/Target/X86/X86ISelLowering.cpp
View File

@ -235,7 +235,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
if (!Subtarget->isTargetDarwin() &&
!Subtarget->isTargetELF() &&
!Subtarget->isTargetCygMing())
setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
setOperationAction(ISD::LABEL, MVT::Other, Expand);
// VASTART needs to be custom lowered to use the VarArgsFrameIndex
setOperationAction(ISD::VASTART , MVT::Other, Custom);

8
lib/Target/X86/X86InstrInfo.cpp
View File

@ -26,14 +26,6 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
TM(tm), RI(tm, *this) {
}
/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
/// instruction if it has one. This is used by codegen passes that update
/// DWARF line number info as they modify the code.
unsigned X86InstrInfo::getDWARF_LABELOpcode() const {
return X86::DWARF_LABEL;
}
bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {

5
lib/Target/X86/X86InstrInfo.h
View File

@ -237,11 +237,6 @@ public:
unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
/// instruction if it has one. This is used by codegen passes that update
/// DWARF line number info as they modify the code.
virtual unsigned getDWARF_LABELOpcode() const;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
/// may be able to convert a two-address instruction into a true

4
lib/Target/X86/X86InstrInfo.td
View File

@ -2449,10 +2449,6 @@ def DWARF_LOC : I<0, Pseudo, (ops i32imm:$line, i32imm:$col, i32imm:$file),
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
(i32 imm:$file))]>;
def DWARF_LABEL : I<0, Pseudo, (ops i32imm:$id),
"\n${:private}debug_loc${id:debug}:",
[(dwarf_label (i32 imm:$id))]>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
//===----------------------------------------------------------------------===//

4
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -1026,7 +1026,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
if (hasInfo) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = DebugInfo->NextLabelID();
BuildMI(MBB, MBBI, TII.get(X86::DWARF_LABEL)).addImm(FrameLabelId);
BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId);
}
if (hasFP(MF)) {
@ -1078,7 +1078,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = DebugInfo->NextLabelID();
BuildMI(MBB, MBBI, TII.get(X86::DWARF_LABEL)).addImm(ReadyLabelId);
BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId);
MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
MachineLocation FPSrc(MachineLocation::VirtualFP);