llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-08 21:32:39 +00:00

History

Evan Cheng cb0f06e05c Disable folding loads into tail call in 32-bit PIC mode. It can introduce illegal code like this:

addl    $12, %esp
        popl    %esi
        popl    %edi
        popl    %ebx
        popl    %ebp
        jmpl    *__Block_deallocator-L1$pb(%esi)  # TAILCALL

The problem is the global base register is assigned GR32 register class. TCRETURNmi needs the registers making up the address mode to have the GR32_TC register class.

The *proper* fix is for X86DAGToDAGISel::getGlobalBaseReg() to return a copy from the global base register of the machine function rather than returning the register itself. But that has the potential of causing it to be coalesced to a more restrictive register class: GR32_TC. It can introduce additional copies and spills. For something as important the PIC base, it's not worth it especially since this is not an issue on 64-bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99455 91177308-0d34-0410-b5e6-96231b3b80d8

2010-03-25 00:10:31 +00:00

Analysis

Finally land the InvokeInst operand reordering.

2010-03-24 13:21:49 +00:00