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39cf555429
Finish the job that was abandoned in D6958 following the refactoring in http://reviews.llvm.org/rL230221: 1. Uncomment the intrinsic def for the AVX r_Int instruction. 2. Add missing r_Int entries to the load folding tables; there are already tests that check these in "test/Codegen/X86/fold-load-unops.ll", so I haven't added any more in this patch. 3. Add patterns to solve PR21507 ( https://llvm.org/bugs/show_bug.cgi?id=21507 ). So instead of this: movaps %xmm0, %xmm1 rcpss %xmm1, %xmm1 movss %xmm1, %xmm0 We should now get: rcpss %xmm0, %xmm0 And instead of this: vsqrtss %xmm0, %xmm0, %xmm1 vblendps $1, %xmm1, %xmm0, %xmm0 ## xmm0 = xmm1[0],xmm0[1,2,3] We should now get: vsqrtss %xmm0, %xmm0, %xmm0 Differential Revision: http://reviews.llvm.org/D9504 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236740 91177308-0d34-0410-b5e6-96231b3b80d8
74 lines
2.4 KiB
LLVM
74 lines
2.4 KiB
LLVM
; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse2 < %s | FileCheck --check-prefix=SSE %s
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse4.1 < %s | FileCheck --check-prefix=SSE %s
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx < %s | FileCheck --check-prefix=AVX %s
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; PR21507 - https://llvm.org/bugs/show_bug.cgi?id=21507
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; Each function should be a single math op; no extra moves.
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define <4 x float> @recip(<4 x float> %x) {
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; SSE-LABEL: recip:
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; SSE: # BB#0:
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; SSE-NEXT: rcpss %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: recip:
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; AVX: # BB#0:
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; AVX-NEXT: vrcpss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%y = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %x)
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%shuf = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %shuf
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}
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define <4 x float> @recip_square_root(<4 x float> %x) {
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; SSE-LABEL: recip_square_root:
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; SSE: # BB#0:
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; SSE-NEXT: rsqrtss %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: recip_square_root:
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; AVX: # BB#0:
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; AVX-NEXT: vrsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%y = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %x)
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%shuf = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %shuf
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}
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define <4 x float> @square_root(<4 x float> %x) {
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; SSE-LABEL: square_root:
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; SSE: # BB#0:
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; SSE-NEXT: sqrtss %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: square_root:
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; AVX: # BB#0:
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%y = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %x)
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%shuf = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %shuf
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}
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define <2 x double> @square_root_double(<2 x double> %x) {
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; SSE-LABEL: square_root_double:
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; SSE: # BB#0:
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; SSE-NEXT: sqrtsd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: square_root_double:
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; AVX: # BB#0:
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; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: retq
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%y = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %x)
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%shuf = shufflevector <2 x double> %y, <2 x double> %x, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %shuf
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}
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declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>)
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declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>)
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declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>)
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declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>)
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