Bill Schmidt 202b6045bf [PowerPC] Implement the vclz instructions for PWR8 ... Patch by Kit Barton. Add the vector count leading zeros instruction for byte, halfword, word, and doubleword sizes. This is a fairly straightforward addition after the changes made for vpopcnt: 1. Add the correct definitions for the various instructions in PPCInstrAltivec.td 2. Make the CTLZ operation legal on vector types when using P8Altivec in PPCISelLowering.cpp Test Plan Created new test case in test/CodeGen/PowerPC/vec_clz.ll to check the instructions are being generated when the CTLZ operation is used in LLVM. Check the encoding and decoding in test/MC/PowerPC/ppc_encoding_vmx.s and test/Disassembler/PowerPC/ppc_encoding_vmx.txt respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228301 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-05 15:24:47 +00:00
..
AArch64	MachineCSE: Clear dead-def flag on CSE.	2015-02-04 19:35:16 +00:00
ARM	[ARM] Use patterns instead of hardcoded regs in test. NFC.	2015-02-05 01:52:19 +00:00
BPF
CPP
Generic	overloaded-intrinsic-name: exercise anyptr on struct	2015-01-27 20:03:08 +00:00
Hexagon	[Hexagon] Adding encoding information for absolute-reg mode stores. Xfailing a test until constant extenders are correctly put in the same packet.	2015-02-04 17:52:06 +00:00
Inputs
Mips	[mips][microMIPS] Implement CodeGen support for SW16 and LW16 instructions	2015-02-04 15:43:17 +00:00
MSP430
NVPTX	[NVPTX] Emit .pragma "nounroll" for loops marked with nounroll	2015-02-01 02:27:45 +00:00
PowerPC	[PowerPC] Implement the vclz instructions for PWR8	2015-02-05 15:24:47 +00:00
R600	R600/SI: Fix i64 truncate to i1	2015-02-05 06:05:13 +00:00
SPARC
SystemZ	Use the integrated assembler as default on SystemZ	2015-01-13 19:45:16 +00:00
Thumb	IR: Move MDLocation into place	2015-01-14 22:27:36 +00:00
Thumb2	[ARM] Fix a bug in constant island pass that was triggering an assertion.	2015-01-08 20:44:50 +00:00
X86	[X86][MMX] Handle i32->mmx conversion using movd	2015-02-05 13:23:07 +00:00
XCore