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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56937 91177308-0d34-0410-b5e6-96231b3b80d8
252 lines
8.1 KiB
C++
252 lines
8.1 KiB
C++
//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LLVMTargetMachine class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/PassManager.h"
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#include "llvm/Pass.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/Analysis/LoopPass.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/GCStrategy.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace llvm {
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bool EnableFastISel;
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}
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static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
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cl::desc("Print LLVM IR produced by the loop-reduce pass"));
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static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
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cl::desc("Print LLVM IR input to isel pass"));
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static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
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cl::desc("Dump emitter generated instructions as assembly"));
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static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
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cl::desc("Dump garbage collector data"));
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// Hidden options to help debugging
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static cl::opt<bool>
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EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
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cl::desc("Perform sinking on machine code"));
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static cl::opt<bool>
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EnableLICM("machine-licm",
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cl::init(false), cl::Hidden,
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cl::desc("Perform loop-invariant code motion on machine code"));
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// When this works it will be on by default.
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static cl::opt<bool>
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DisablePostRAScheduler("disable-post-RA-scheduler",
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cl::desc("Disable scheduling after register allocation"),
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cl::init(true));
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// Enable or disable FastISel. Both options are needed, because
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// FastISel is enabled by default with -fast, and we wish to be
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// able to enable or disable fast-isel independently from -fast.
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static cl::opt<bool>
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EnableFastISelOption("fast-isel", cl::Hidden,
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cl::desc("Enable the experimental \"fast\" instruction selector"));
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static cl::opt<bool>
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DisableFastISelOption("disable-fast-isel", cl::Hidden,
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cl::desc("Disable the experimental \"fast\" instruction selector"));
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FileModel::Model
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LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
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raw_ostream &Out,
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CodeGenFileType FileType,
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bool Fast) {
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// Add common CodeGen passes.
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if (addCommonCodeGenPasses(PM, Fast))
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return FileModel::Error;
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// Fold redundant debug labels.
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PM.add(createDebugLabelFoldingPass());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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if (addPreEmitPass(PM, Fast) && PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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if (!Fast)
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PM.add(createLoopAlignerPass());
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switch (FileType) {
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default:
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break;
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case TargetMachine::AssemblyFile:
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if (addAssemblyEmitter(PM, Fast, Out))
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return FileModel::Error;
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return FileModel::AsmFile;
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case TargetMachine::ObjectFile:
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if (getMachOWriterInfo())
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return FileModel::MachOFile;
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else if (getELFWriterInfo())
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return FileModel::ElfFile;
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}
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return FileModel::Error;
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}
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/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
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/// be split up (e.g., to add an object writer pass), this method can be used to
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/// finish up adding passes to emit the file, if necessary.
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bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
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MachineCodeEmitter *MCE,
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bool Fast) {
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if (MCE)
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addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
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PM.add(createGCInfoDeleter());
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// Delete machine code for this function
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PM.add(createMachineCodeDeleter());
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return false; // success!
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}
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
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/// get machine code emitted. This uses a MachineCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method should returns true if machine code emission is
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/// not supported.
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///
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bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
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MachineCodeEmitter &MCE,
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bool Fast) {
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// Add common CodeGen passes.
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if (addCommonCodeGenPasses(PM, Fast))
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return true;
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if (addPreEmitPass(PM, Fast) && PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
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PM.add(createGCInfoDeleter());
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// Delete machine code for this function
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PM.add(createMachineCodeDeleter());
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return false; // success!
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}
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/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
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/// both emitting to assembly files or machine code output.
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///
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bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
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// Standard LLVM-Level Passes.
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// Run loop strength reduction before anything else.
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if (!Fast) {
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PM.add(createLoopStrengthReducePass(getTargetLowering()));
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if (PrintLSR)
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PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
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}
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PM.add(createGCLoweringPass());
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if (!getTargetAsmInfo()->doesSupportExceptionHandling())
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PM.add(createLowerInvokePass(getTargetLowering()));
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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if (!Fast)
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PM.add(createCodeGenPreparePass(getTargetLowering()));
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if (PrintISelInput)
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PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
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&cerr));
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// Standard Lower-Level Passes.
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// Enable FastISel with -fast, but allow that to be overridden.
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assert((!EnableFastISelOption || !DisableFastISelOption) &&
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"Both -fast-isel and -disable-fast-isel given!");
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if (EnableFastISelOption ||
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(Fast && !DisableFastISelOption))
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EnableFastISel = true;
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// Ask the target for an isel.
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if (addInstSelector(PM, Fast))
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return true;
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// Print the instruction selected machine code...
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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// If we're using Fast-ISel, clean up the mess.
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if (EnableFastISel)
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PM.add(createDeadMachineInstructionElimPass());
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if (EnableLICM)
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PM.add(createMachineLICMPass());
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if (EnableSinking)
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PM.add(createMachineSinkingPass());
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// Run pre-ra passes.
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if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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// Perform register allocation.
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PM.add(createRegisterAllocator());
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// Perform stack slot coloring.
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if (!Fast)
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PM.add(createStackSlotColoringPass());
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if (PrintMachineCode) // Print the register-allocated code
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PM.add(createMachineFunctionPrinterPass(cerr));
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// Run post-ra passes.
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if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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PM.add(createLowerSubregsPass());
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if (PrintMachineCode) // Print the subreg lowered code
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PM.add(createMachineFunctionPrinterPass(cerr));
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// Insert prolog/epilog code. Eliminate abstract frame index references...
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PM.add(createPrologEpilogCodeInserter());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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// Second pass scheduler.
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if (!Fast && !DisablePostRAScheduler)
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PM.add(createPostRAScheduler());
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// Branch folding must be run after regalloc and prolog/epilog insertion.
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if (!Fast)
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PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
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PM.add(createGCMachineCodeAnalysisPass());
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(cerr));
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if (PrintGCInfo)
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PM.add(createGCInfoPrinter(*cerr));
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return false;
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}
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