Evan Cheng 22a529990b If two instructions are both two-address code, favors (schedule closer to ... terminator) the one that has a CopyToReg use. This fixes 2006-05-11-InstrSched.ll with -new-cc-modeling-scheme. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42453 91177308-0d34-0410-b5e6-96231b3b80d8		2007-09-28 22:32:30 +00:00
..
CallingConvLower.cpp
DAGCombiner.cpp
LegalizeDAG.cpp	Fix long double -> uint64 conversion.	2007-09-28 18:44:17 +00:00
Makefile
ScheduleDAG.cpp	If two instructions are both two-address code, favors (schedule closer to	2007-09-28 22:32:30 +00:00
ScheduleDAGList.cpp	Trim some unneeded fields.	2007-09-28 19:24:24 +00:00
ScheduleDAGRRList.cpp	If two instructions are both two-address code, favors (schedule closer to	2007-09-28 22:32:30 +00:00
ScheduleDAGSimple.cpp	Allow copyRegToReg to emit cross register classes copies.	2007-09-26 06:25:56 +00:00
SelectionDAG.cpp	Change APFloat::convertFromInteger to take the incoming	2007-09-21 22:09:37 +00:00
SelectionDAGISel.cpp	Add sqrt and powi intrinsics for long double.	2007-09-28 01:08:20 +00:00
SelectionDAGPrinter.cpp	Added major new capabilities to scheduler (only BURR for now) to support physical register dependency. The BURR scheduler can now backtrace and duplicate instructions in order to avoid "expensive / impossible to copy" values (e.g. status flag EFLAGS for x86) from being clobbered.	2007-09-25 01:54:36 +00:00
TargetLowering.cpp	Add sqrt and powi intrinsics for long double.	2007-09-28 01:08:20 +00:00