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llvm-6502/lib/Target/XCore
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Rafael Espindola 26c8dcc692 Always compute all the bits in ComputeMaskedBits. 
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04 12:51:34 +00:00
..
MCTargetDesc Prune some includes 2012-03-27 07:54:11 +00:00
TargetInfo LLVMBuild: Remove trailing newline, which irked me. 2011-12-12 19:48:00 +00:00
CMakeLists.txt Fix up the CMake build for the new files added in r146960, they're 2011-12-20 08:42:11 +00:00
LLVMBuild.txt LLVMBuild: Introduce a common section which currently has a list of the 2011-12-12 22:45:54 +00:00
Makefile Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
README.txt
XCore.h Pass optLevel to XCoreDAGToDAGISel. 2011-12-15 15:18:35 +00:00
XCore.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreAsmPrinter.cpp Implement the emitFrameIndexDebugValue and getDebugValueLocation hooks. 2011-10-11 12:55:35 +00:00
XCoreCallingConv.td Add support for trampolines on the XCore. 2011-02-02 14:57:41 +00:00
XCoreFrameLowering.cpp Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
XCoreFrameLowering.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreInstrFormats.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreInstrInfo.cpp Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
XCoreInstrInfo.h Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
XCoreInstrInfo.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreISelDAGToDAG.cpp Pass optLevel to XCoreDAGToDAGISel. 2011-12-15 15:18:35 +00:00
XCoreISelLowering.cpp Always compute all the bits in ComputeMaskedBits. 2012-04-04 12:51:34 +00:00
XCoreISelLowering.h Always compute all the bits in ComputeMaskedBits. 2012-04-04 12:51:34 +00:00
XCoreMachineFunctionInfo.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreMachineFunctionInfo.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreRegisterInfo.cpp Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
XCoreRegisterInfo.h Remove unused functions getArgRegs and getNumArgRegs. 2012-03-11 06:46:40 +00:00
XCoreRegisterInfo.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreSelectionDAGInfo.cpp
XCoreSelectionDAGInfo.h
XCoreSubtarget.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreSubtarget.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreTargetMachine.cpp TargetPassConfig: confine the MC configuration to TargetMachine. 2012-02-04 02:56:59 +00:00
XCoreTargetMachine.h Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
XCoreTargetObjectFile.cpp Remove more duplicated code. 2011-01-23 04:43:11 +00:00
XCoreTargetObjectFile.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00

README.txt 

To-do
-----

* Instruction encodings
* Tailcalls
* Investigate loop alignment
* Add builtins