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precisely track pressure on a selection DAG, but we can at least keep it balanced. This design accounts for various interesting aspects of selection DAGS: register and subregister copies, glued nodes, dead nodes, unused registers, etc. Added SUnit::NumRegDefsLeft and ScheduleDAGSDNodes::RegDefIter. Note: I disabled PrescheduleNodesWithMultipleUses when register pressure is enabled, based on no evidence other than I don't think it makes sense to have both enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124853 91177308-0d34-0410-b5e6-96231b3b80d8
152 lines
5.3 KiB
C++
152 lines
5.3 KiB
C++
//===---- ScheduleDAGSDNodes.h - SDNode Scheduling --------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ScheduleDAGSDNodes class, which implements
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// scheduling for an SDNode-based dependency graph.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SCHEDULEDAGSDNODES_H
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#define SCHEDULEDAGSDNODES_H
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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namespace llvm {
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/// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
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///
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/// Edges between SUnits are initially based on edges in the SelectionDAG,
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/// and additional edges can be added by the schedulers as heuristics.
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/// SDNodes such as Constants, Registers, and a few others that are not
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/// interesting to schedulers are not allocated SUnits.
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///
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/// SDNodes with MVT::Glue operands are grouped along with the flagged
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/// nodes into a single SUnit so that they are scheduled together.
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///
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/// SDNode-based scheduling graphs do not use SDep::Anti or SDep::Output
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/// edges. Physical register dependence information is not carried in
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/// the DAG and must be handled explicitly by schedulers.
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///
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class ScheduleDAGSDNodes : public ScheduleDAG {
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public:
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SelectionDAG *DAG; // DAG of the current basic block
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const InstrItineraryData *InstrItins;
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explicit ScheduleDAGSDNodes(MachineFunction &mf);
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virtual ~ScheduleDAGSDNodes() {}
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/// Run - perform scheduling.
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///
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void Run(SelectionDAG *dag, MachineBasicBlock *bb,
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MachineBasicBlock::iterator insertPos);
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/// isPassiveNode - Return true if the node is a non-scheduled leaf.
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///
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static bool isPassiveNode(SDNode *Node) {
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if (isa<ConstantSDNode>(Node)) return true;
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if (isa<ConstantFPSDNode>(Node)) return true;
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if (isa<RegisterSDNode>(Node)) return true;
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if (isa<GlobalAddressSDNode>(Node)) return true;
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if (isa<BasicBlockSDNode>(Node)) return true;
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if (isa<FrameIndexSDNode>(Node)) return true;
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if (isa<ConstantPoolSDNode>(Node)) return true;
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if (isa<JumpTableSDNode>(Node)) return true;
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if (isa<ExternalSymbolSDNode>(Node)) return true;
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if (isa<BlockAddressSDNode>(Node)) return true;
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if (Node->getOpcode() == ISD::EntryToken ||
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isa<MDNodeSDNode>(Node)) return true;
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return false;
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}
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/// NewSUnit - Creates a new SUnit and return a ptr to it.
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///
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SUnit *NewSUnit(SDNode *N);
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/// Clone - Creates a clone of the specified SUnit. It does not copy the
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/// predecessors / successors info nor the temporary scheduling states.
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///
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SUnit *Clone(SUnit *N);
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/// BuildSchedGraph - Build the SUnit graph from the selection dag that we
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/// are input. This SUnit graph is similar to the SelectionDAG, but
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/// excludes nodes that aren't interesting to scheduling, and represents
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/// flagged together nodes with a single SUnit.
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virtual void BuildSchedGraph(AliasAnalysis *AA);
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/// InitNumRegDefsLeft - Determine the # of regs defined by this node.
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///
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void InitNumRegDefsLeft(SUnit *SU);
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/// ComputeLatency - Compute node latency.
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///
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virtual void ComputeLatency(SUnit *SU);
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/// ComputeOperandLatency - Override dependence edge latency using
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/// operand use/def information
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///
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virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use,
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SDep& dep) const { }
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virtual void ComputeOperandLatency(SDNode *Def, SDNode *Use,
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unsigned OpIdx, SDep& dep) const;
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virtual MachineBasicBlock *EmitSchedule();
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/// Schedule - Order nodes according to selected style, filling
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/// in the Sequence member.
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///
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virtual void Schedule() = 0;
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virtual void dumpNode(const SUnit *SU) const;
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virtual std::string getGraphNodeLabel(const SUnit *SU) const;
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virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
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/// RegDefIter - In place iteration over the values defined by an
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/// SUnit. This does not need copies of the iterator or any other STLisms.
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/// The iterator creates itself, rather than being provided by the SchedDAG.
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class RegDefIter {
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const ScheduleDAGSDNodes *SchedDAG;
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const SDNode *Node;
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unsigned DefIdx;
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unsigned NodeNumDefs;
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EVT ValueType;
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public:
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RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
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bool IsValid() const { return Node != NULL; }
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EVT GetValue() const {
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assert(IsValid() && "bad iterator");
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return ValueType;
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}
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void Advance();
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private:
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void InitNodeNumDefs();
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};
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private:
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/// ClusterNeighboringLoads - Cluster loads from "near" addresses into
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/// combined SUnits.
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void ClusterNeighboringLoads(SDNode *Node);
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/// ClusterNodes - Cluster certain nodes which should be scheduled together.
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///
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void ClusterNodes();
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/// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.
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void BuildSchedUnits();
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void AddSchedEdges();
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};
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}
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#endif
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