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https://github.com/c64scene-ar/llvm-6502.git
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8b2b8a1835
This update was done with the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
fi
done
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
2.2 KiB
LLVM
100 lines
2.2 KiB
LLVM
; Test 32-bit GPR accesses to a PC-relative location.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@gsrc16 = global i16 1
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@gsrc32 = global i32 1
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@gdst16 = global i16 2
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@gdst32 = global i32 2
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@gsrc16u = global i16 1, align 1, section "foo"
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@gsrc32u = global i32 1, align 2, section "foo"
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@gdst16u = global i16 2, align 1, section "foo"
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@gdst32u = global i32 2, align 2, section "foo"
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; Check sign-extending loads from i16.
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define i32 @f1() {
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; CHECK-LABEL: f1:
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; CHECK: lhrl %r2, gsrc16
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; CHECK: br %r14
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%val = load i16 *@gsrc16
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%ext = sext i16 %val to i32
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ret i32 %ext
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}
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; Check zero-extending loads from i16.
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define i32 @f2() {
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; CHECK-LABEL: f2:
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; CHECK: llhrl %r2, gsrc16
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; CHECK: br %r14
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%val = load i16 *@gsrc16
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%ext = zext i16 %val to i32
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ret i32 %ext
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}
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; Check truncating 16-bit stores.
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define void @f3(i32 %val) {
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; CHECK-LABEL: f3:
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; CHECK: sthrl %r2, gdst16
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; CHECK: br %r14
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%half = trunc i32 %val to i16
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store i16 %half, i16 *@gdst16
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ret void
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}
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; Check plain loads and stores.
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define void @f4() {
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; CHECK-LABEL: f4:
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; CHECK: lrl %r0, gsrc32
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; CHECK: strl %r0, gdst32
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; CHECK: br %r14
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%val = load i32 *@gsrc32
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store i32 %val, i32 *@gdst32
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ret void
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}
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; Repeat f1 with an unaligned variable.
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define i32 @f5() {
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; CHECK-LABEL: f5:
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; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
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; CHECK: lh %r2, 0([[REG]])
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; CHECK: br %r14
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%val = load i16 *@gsrc16u, align 1
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%ext = sext i16 %val to i32
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ret i32 %ext
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}
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; Repeat f2 with an unaligned variable.
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define i32 @f6() {
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; CHECK-LABEL: f6:
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; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
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; CHECK: llh %r2, 0([[REG]])
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; CHECK: br %r14
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%val = load i16 *@gsrc16u, align 1
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%ext = zext i16 %val to i32
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ret i32 %ext
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}
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; Repeat f3 with an unaligned variable.
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define void @f7(i32 %val) {
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; CHECK-LABEL: f7:
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; CHECK: lgrl [[REG:%r[0-5]]], gdst16u
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; CHECK: sth %r2, 0([[REG]])
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; CHECK: br %r14
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%half = trunc i32 %val to i16
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store i16 %half, i16 *@gdst16u, align 1
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ret void
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}
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; Repeat f4 with unaligned variables.
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define void @f8() {
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; CHECK-LABEL: f8:
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; CHECK: larl [[REG:%r[0-5]]], gsrc32u
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; CHECK: l [[VAL:%r[0-5]]], 0([[REG]])
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; CHECK: larl [[REG:%r[0-5]]], gdst32u
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; CHECK: st [[VAL]], 0([[REG]])
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; CHECK: br %r14
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%val = load i32 *@gsrc32u, align 2
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store i32 %val, i32 *@gdst32u, align 2
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ret void
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}
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