Jyoti Allur 245caec9b3 This patch fixes issue with lowering below mentioned pattern :- ... _foo: smull r0, r1, r1, r0 smull r2, r3, r3, r2 adds r0, r2, r0 adc r1, r3, r1 bx lr to _foo: smull r0, r1, r1, r0 smlal r0, r1, r3, r2 bx lr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226904 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-23 09:10:03 +00:00
..
AArch64	DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N))	2015-01-21 23:17:19 +00:00
ARM	This patch fixes issue with lowering below mentioned pattern :-	2015-01-23 09:10:03 +00:00
CPP
Generic
Hexagon	[Hexagon] Converting multiply and accumulate with immediate intrinsics to patterns.	2015-01-21 18:13:15 +00:00
Inputs
Mips	[mips] Add registers and ALL check prefix to octeon test case.	2015-01-20 16:14:02 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add r2 as an operand for all calls under both PPC64 ELF V1 and V2	2015-01-19 07:20:27 +00:00
R600	R600: Try to use lower types for 64bit division if possible	2015-01-22 23:42:43 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	[x86] Change u8imm operands to always print as unsigned. This makes shuffle masks and the like make way more sense.	2015-01-23 08:00:59 +00:00
XCore