Manman Ren 247c5ab07c ARM: peephole optimization to remove cmp instruction ... This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156599 91177308-0d34-0410-b5e6-96231b3b80d8		2012-05-11 01:30:47 +00:00
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ARM	ARM: peephole optimization to remove cmp instruction	2012-05-11 01:30:47 +00:00
CellSPU
CPP
Generic	change the objectsize intrinsic signature: add a 3rd parameter to denote the maximum runtime performance penalty that the user is willing to accept.	2012-05-09 15:52:43 +00:00
Hexagon	Hexagon V5 FP Support.	2012-05-10 20:20:25 +00:00
MBlaze
Mips	Add support for the 'X' inline asm operand modifier.	2012-05-10 21:48:22 +00:00
MSP430
NVPTX	This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.	2012-05-04 20:18:50 +00:00
PowerPC
PTX
SPARC
Thumb
Thumb2	Added a regress test for the bug #9964 before close it.	2012-05-09 19:07:04 +00:00
X86	Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),	2012-05-11 00:19:32 +00:00
XCore