llvm-6502/test/CodeGen
Matt Arsenault 257e85e7c2 R600: Custom lower frem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217553 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-10 21:44:27 +00:00
..
AArch64 [AArch64] Temporarily desactivate the PBQP test, while I investigate some leaks in the allocator 2014-09-10 18:40:18 +00:00
ARM ARM: don't size-reduce STMs using the LR register. 2014-09-10 12:53:28 +00:00
CPP IR: add "cmpxchg weak" variant to support permitted failure. 2014-06-13 14:24:07 +00:00
Generic
Hexagon
Inputs
Mips
MSP430 Drop the W postfix on the 16-bit registers. 2014-09-10 06:58:14 +00:00
NVPTX
PowerPC
R600 R600: Custom lower frem 2014-09-10 21:44:27 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86
XCore