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https://github.com/c64scene-ar/llvm-6502.git
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ad5c880892
We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158302 91177308-0d34-0410-b5e6-96231b3b80d8
552 lines
22 KiB
C++
552 lines
22 KiB
C++
//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that ARM uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMISELLOWERING_H
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#define ARMISELLOWERING_H
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#include "ARM.h"
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#include "ARMSubtarget.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include <vector>
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namespace llvm {
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class ARMConstantPoolValue;
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namespace ARMISD {
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// ARM Specific DAG Nodes
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enum NodeType {
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// Start the numbering where the builtin ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
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// TargetExternalSymbol, and TargetGlobalAddress.
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WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
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// DYN mode.
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WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
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// PIC mode.
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WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
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// Add pseudo op to model memcpy for struct byval.
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COPY_STRUCT_BYVAL,
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CALL, // Function call.
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CALL_PRED, // Function call that's predicable.
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CALL_NOLINK, // Function call with branch not branch-and-link.
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tCALL, // Thumb function call.
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BRCOND, // Conditional branch.
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BR_JT, // Jumptable branch.
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BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
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RET_FLAG, // Return with a flag operand.
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PIC_ADD, // Add with a PC operand and a PIC label.
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CMP, // ARM compare instructions.
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CMN, // ARM CMN instructions.
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CMPZ, // ARM compare that sets only Z flag.
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CMPFP, // ARM VFP compare instruction, sets FPSCR.
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CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
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FMSTAT, // ARM fmstat instruction.
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CMOV, // ARM conditional move instructions.
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CAND, // ARM conditional and instructions.
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COR, // ARM conditional or instructions.
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CXOR, // ARM conditional xor instructions.
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BCC_i64,
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RBIT, // ARM bitreverse instruction
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FTOSI, // FP to sint within a FP register.
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FTOUI, // FP to uint within a FP register.
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SITOF, // sint to FP within a FP register.
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UITOF, // uint to FP within a FP register.
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SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
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SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
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RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
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ADDC, // Add with carry
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ADDE, // Add using carry
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SUBC, // Sub with carry
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SUBE, // Sub using carry
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VMOVRRD, // double to two gprs.
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VMOVDRR, // Two gprs to double.
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EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
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EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
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TC_RETURN, // Tail call return pseudo.
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THREAD_POINTER,
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DYN_ALLOC, // Dynamic allocation on the stack.
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MEMBARRIER, // Memory barrier (DMB)
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MEMBARRIER_MCR, // Memory barrier (MCR)
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PRELOAD, // Preload
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VCEQ, // Vector compare equal.
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VCEQZ, // Vector compare equal to zero.
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VCGE, // Vector compare greater than or equal.
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VCGEZ, // Vector compare greater than or equal to zero.
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VCLEZ, // Vector compare less than or equal to zero.
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VCGEU, // Vector compare unsigned greater than or equal.
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VCGT, // Vector compare greater than.
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VCGTZ, // Vector compare greater than zero.
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VCLTZ, // Vector compare less than zero.
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VCGTU, // Vector compare unsigned greater than.
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VTST, // Vector test bits.
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// Vector shift by immediate:
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VSHL, // ...left
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VSHRs, // ...right (signed)
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VSHRu, // ...right (unsigned)
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VSHLLs, // ...left long (signed)
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VSHLLu, // ...left long (unsigned)
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VSHLLi, // ...left long (with maximum shift count)
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VSHRN, // ...right narrow
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// Vector rounding shift by immediate:
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VRSHRs, // ...right (signed)
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VRSHRu, // ...right (unsigned)
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VRSHRN, // ...right narrow
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// Vector saturating shift by immediate:
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VQSHLs, // ...left (signed)
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VQSHLu, // ...left (unsigned)
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VQSHLsu, // ...left (signed to unsigned)
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VQSHRNs, // ...right narrow (signed)
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VQSHRNu, // ...right narrow (unsigned)
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VQSHRNsu, // ...right narrow (signed to unsigned)
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// Vector saturating rounding shift by immediate:
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VQRSHRNs, // ...right narrow (signed)
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VQRSHRNu, // ...right narrow (unsigned)
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VQRSHRNsu, // ...right narrow (signed to unsigned)
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// Vector shift and insert:
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VSLI, // ...left
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VSRI, // ...right
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// Vector get lane (VMOV scalar to ARM core register)
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// (These are used for 8- and 16-bit element types only.)
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VGETLANEu, // zero-extend vector extract element
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VGETLANEs, // sign-extend vector extract element
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// Vector move immediate and move negated immediate:
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VMOVIMM,
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VMVNIMM,
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// Vector move f32 immediate:
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VMOVFPIMM,
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// Vector duplicate:
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VDUP,
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VDUPLANE,
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// Vector shuffles:
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VEXT, // extract
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VREV64, // reverse elements within 64-bit doublewords
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VREV32, // reverse elements within 32-bit words
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VREV16, // reverse elements within 16-bit halfwords
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VZIP, // zip (interleave)
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VUZP, // unzip (deinterleave)
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VTRN, // transpose
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VTBL1, // 1-register shuffle with mask
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VTBL2, // 2-register shuffle with mask
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// Vector multiply long:
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VMULLs, // ...signed
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VMULLu, // ...unsigned
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// Operands of the standard BUILD_VECTOR node are not legalized, which
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// is fine if BUILD_VECTORs are always lowered to shuffles or other
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// operations, but for ARM some BUILD_VECTORs are legal as-is and their
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// operands need to be legalized. Define an ARM-specific version of
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// BUILD_VECTOR for this purpose.
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BUILD_VECTOR,
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// Floating-point max and min:
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FMAX,
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FMIN,
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// Bit-field insert
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BFI,
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// Vector OR with immediate
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VORRIMM,
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// Vector AND with NOT of immediate
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VBICIMM,
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// Vector bitwise select
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VBSL,
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// Vector load N-element structure to all lanes:
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VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
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VLD3DUP,
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VLD4DUP,
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// NEON loads with post-increment base updates:
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VLD1_UPD,
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VLD2_UPD,
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VLD3_UPD,
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VLD4_UPD,
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VLD2LN_UPD,
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VLD3LN_UPD,
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VLD4LN_UPD,
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VLD2DUP_UPD,
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VLD3DUP_UPD,
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VLD4DUP_UPD,
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// NEON stores with post-increment base updates:
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VST1_UPD,
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VST2_UPD,
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VST3_UPD,
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VST4_UPD,
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VST2LN_UPD,
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VST3LN_UPD,
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VST4LN_UPD,
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// 64-bit atomic ops (value split into two registers)
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ATOMADD64_DAG,
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ATOMSUB64_DAG,
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ATOMOR64_DAG,
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ATOMXOR64_DAG,
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ATOMAND64_DAG,
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ATOMNAND64_DAG,
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ATOMSWAP64_DAG,
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ATOMCMPXCHG64_DAG
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};
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}
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/// Define some predicates that are used for node matching.
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namespace ARM {
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bool isBitFieldInvertedMask(unsigned v);
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}
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//===--------------------------------------------------------------------===//
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// ARMTargetLowering - ARM Implementation of the TargetLowering interface
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class ARMTargetLowering : public TargetLowering {
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public:
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explicit ARMTargetLowering(TargetMachine &TM);
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virtual unsigned getJumpTableEncoding(void) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/// ReplaceNodeResults - Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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///
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virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const;
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// getSetCCResultType - Return the value type to use for ISD::SETCC.
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virtual EVT getSetCCResultType(EVT VT) const;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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virtual void
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AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
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SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
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/// allowsUnalignedMemoryAccesses - Returns true if the target allows
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/// unaligned memory accesses. of the specified type.
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virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
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virtual EVT getOptimalMemOpType(uint64_t Size,
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unsigned DstAlign, unsigned SrcAlign,
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bool IsZeroVal,
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bool MemcpyStrSrc,
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MachineFunction &MF) const;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
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bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
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/// isLegalICmpImmediate - Return true if the specified immediate is legal
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/// icmp immediate, that is the target has icmp instructions which can
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/// compare a register against the immediate without having to materialize
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/// the immediate into a register.
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virtual bool isLegalICmpImmediate(int64_t Imm) const;
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/// isLegalAddImmediate - Return true if the specified immediate is legal
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/// add immediate, that is the target has add instructions which can
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/// add a register and the immediate without having to materialize
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/// the immediate into a register.
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virtual bool isLegalAddImmediate(int64_t Imm) const;
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/// getPreIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if the node's address
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/// can be legally represented as pre-indexed load / store address.
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virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
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SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const;
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/// getPostIndexedAddressParts - returns true by value, base pointer and
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/// offset pointer and addressing mode by reference if this node can be
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/// combined with a load / store to form a post-indexed load / store.
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virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
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SDValue &Base, SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const;
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virtual void computeMaskedBitsForTargetNode(const SDValue Op,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth) const;
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virtual bool ExpandInlineAsm(CallInst *CI) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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ConstraintWeight getSingleConstraintMatchWeight(
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AsmOperandInfo &info, const char *constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
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/// true it means one of the asm constraint of the inline asm instruction
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/// being processed is 'm'.
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virtual void LowerAsmOperandForConstraint(SDValue Op,
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std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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const ARMSubtarget* getSubtarget() const {
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return Subtarget;
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}
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/// getRegClassFor - Return the register class that should be used for the
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/// specified value type.
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virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
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/// getMaximalGlobalOffset - Returns the maximal possible offset which can
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/// be used for loads / stores from the global.
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virtual unsigned getMaximalGlobalOffset() const;
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/// createFastISel - This method returns a target specific FastISel object,
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/// or null if the target does not support "fast" ISel.
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virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
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Sched::Preference getSchedulingPreference(SDNode *N) const;
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bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
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const CallInst &I,
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unsigned Intrinsic) const;
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protected:
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std::pair<const TargetRegisterClass*, uint8_t>
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findRepresentativeClass(EVT VT) const;
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private:
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const ARMSubtarget *Subtarget;
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const TargetRegisterInfo *RegInfo;
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const InstrItineraryData *Itins;
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/// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
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///
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unsigned ARMPCLabelIndex;
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void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
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void addDRTypeForNEON(EVT VT);
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void addQRTypeForNEON(EVT VT);
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typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
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void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
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SDValue Chain, SDValue &Arg,
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RegsToPassVector &RegsToPass,
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CCValAssign &VA, CCValAssign &NextVA,
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SDValue &StackPtr,
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SmallVector<SDValue, 8> &MemOpChains,
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ISD::ArgFlagsTy Flags) const;
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SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
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SDValue &Root, SelectionDAG &DAG,
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DebugLoc dl) const;
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CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
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bool isVarArg) const;
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SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
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DebugLoc dl, SelectionDAG &DAG,
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const CCValAssign &VA,
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ISD::ArgFlagsTy Flags) const;
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SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
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const ARMSubtarget *Subtarget) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
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SelectionDAG &DAG) const;
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SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
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SelectionDAG &DAG,
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TLSModel::Model model) const;
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SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
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const ARMSubtarget *ST) const;
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SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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const ARMSubtarget *ST) const;
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SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
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DebugLoc dl, SDValue &Chain, unsigned ArgOffset)
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const;
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void computeRegArea(CCState &CCInfo, MachineFunction &MF,
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unsigned &VARegSize, unsigned &VARegSaveSize) const;
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virtual SDValue
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LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
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/// HandleByVal - Target-specific cleanup for ByVal support.
|
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virtual void HandleByVal(CCState *, unsigned &) const;
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/// IsEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization. Targets which want to do tail call
|
|
/// optimization should implement this function.
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|
bool IsEligibleForTailCallOptimization(SDValue Callee,
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CallingConv::ID CalleeCC,
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|
bool isVarArg,
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|
bool isCalleeStructRet,
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|
bool isCallerStructRet,
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|
const SmallVectorImpl<ISD::OutputArg> &Outs,
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|
const SmallVectorImpl<SDValue> &OutVals,
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
SelectionDAG& DAG) const;
|
|
virtual SDValue
|
|
LowerReturn(SDValue Chain,
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
|
DebugLoc dl, SelectionDAG &DAG) const;
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|
|
|
virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
|
|
|
|
virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
|
|
|
|
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
|
SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
|
|
SDValue getVFPCmp(SDValue LHS, SDValue RHS,
|
|
SelectionDAG &DAG, DebugLoc dl) const;
|
|
SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
|
|
|
|
SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
|
|
|
|
MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
|
|
MachineBasicBlock *BB,
|
|
unsigned Size) const;
|
|
MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
|
|
MachineBasicBlock *BB,
|
|
unsigned Size,
|
|
unsigned BinOpcode) const;
|
|
MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
|
|
MachineBasicBlock *BB,
|
|
unsigned Op1,
|
|
unsigned Op2,
|
|
bool NeedsCarry = false,
|
|
bool IsCmpxchg = false) const;
|
|
MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
|
|
MachineBasicBlock *BB,
|
|
unsigned Size,
|
|
bool signExtend,
|
|
ARMCC::CondCodes Cond) const;
|
|
|
|
void SetupEntryBlockForSjLj(MachineInstr *MI,
|
|
MachineBasicBlock *MBB,
|
|
MachineBasicBlock *DispatchBB, int FI) const;
|
|
|
|
MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
|
|
MachineBasicBlock *MBB) const;
|
|
|
|
bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
|
|
|
|
MachineBasicBlock *EmitStructByval(MachineInstr *MI,
|
|
MachineBasicBlock *MBB) const;
|
|
};
|
|
|
|
enum NEONModImmType {
|
|
VMOVModImm,
|
|
VMVNModImm,
|
|
OtherModImm
|
|
};
|
|
|
|
|
|
namespace ARM {
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
|
|
}
|
|
}
|
|
|
|
#endif // ARMISELLOWERING_H
|