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269bc0042fc976b13b44c97c6546b4d726073940
llvm-6502/test/CodeGen
T
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Richard Osborne 269bc0042f Add support for ISD::TRAP to the XCore backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60479 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-03 10:59:16 +00:00
..
Alpha
Correct some thinkos in the expansion of ADD/SUB
2008-11-12 08:23:26 +00:00
ARM
- Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction.
2008-11-20 02:32:35 +00:00
CBackend
Fix PR2907 by digging through constant expressions to find FP constants that
2008-10-22 04:53:16 +00:00
CellSPU
CellSPU:
2008-12-02 19:53:53 +00:00
CPP
…
Generic
Test add-with-overflow with fast ISel.
2008-11-24 05:23:38 +00:00
IA64
…
Mips
Fix PR2667: add soft float support for sint_to_fp/uint_to_fp
2008-11-10 17:36:26 +00:00
PowerPC
Remove a (what appears to be) overly strict assertion. Here is what happened:
2008-12-02 21:57:09 +00:00
SPARC
Add testcase for 'r' inline asm operand
2008-10-10 20:28:59 +00:00
X86
Fix test.
2008-12-03 08:20:45 +00:00
XCore
Add support for ISD::TRAP to the XCore backend
2008-12-03 10:59:16 +00:00
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