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Add support for ISD::TRAP to the XCore backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60479 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -106,6 +106,8 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
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setOperationAction(ISD::ROTL , MVT::i32, Expand);
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setOperationAction(ISD::ROTR , MVT::i32, Expand);
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setOperationAction(ISD::TRAP, MVT::Other, Legal);
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// Expand jump tables for now
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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@ -762,7 +762,7 @@ def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
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// One operand short
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// TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp
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// bru, setdp, setcp, setv, setev, kcall, ecallt, ecallf
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// bru, setdp, setcp, setv, setev, kcall
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// dgetreg
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let isBranch=1, isIndirectBranch=1, isTerminator=1 in
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def BAU_1r : _F1R<(outs), (ins GRRegs:$addr),
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@ -774,6 +774,16 @@ def SETSP_1r : _F1R<(outs), (ins GRRegs:$src),
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"set sp, $src",
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[]>;
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let isBarrier = 1, hasCtrlDep = 1 in
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def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src),
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"ecallt $src",
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[]>;
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let isBarrier = 1, hasCtrlDep = 1 in
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def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
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"ecallf $src",
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[]>;
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let isCall=1,
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// All calls clobber the the link register and the non-callee-saved registers:
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Defs = [R0, R1, R2, R3, R11, LR] in {
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@ -852,6 +862,9 @@ def : Pat<(store GRRegs:$val, GRRegs:$addr),
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/// cttz
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def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
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/// trap
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def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
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///
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/// branch patterns
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///
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11
test/CodeGen/XCore/trap.ll
Normal file
11
test/CodeGen/XCore/trap.ll
Normal file
@ -0,0 +1,11 @@
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; RUN: llvm-as < %s | llc -march=xcore > %t1.s
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; RUN: grep "ecallf" %t1.s | count 1
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; RUN: grep "ldc" %t1.s | count 1
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define i32 @test() noreturn nounwind {
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entry:
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tail call void @llvm.trap( )
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unreachable
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}
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declare void @llvm.trap() nounwind
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