mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 17:29:19 +00:00
Silvermont can only decode one instruction per cycle if the instruction exceeds 8 bytes. Also in Silvermont instructions with more than 3 prefixes will cause 3 cycle penalty. Maximum nop length is limited to 7 bytes when used for padding on Silvermont. For other x86 processors max nop length remains unchanged 15 bytes. Differential Revision: http://reviews.llvm.org/D4374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212321 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
1.1 KiB
ArmAsm
26 lines
1.1 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
|
|
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
|
|
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
|
|
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
|
|
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=slm %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=SLM %s
|
|
|
|
# Ensure alignment directives also emit sequences of 15-byte NOPs on processors
|
|
# capable of using long NOPs.
|
|
inc %eax
|
|
.p2align 5
|
|
inc %eax
|
|
# CHECK: 0: inc
|
|
# CHECK-NEXT: 1: nop
|
|
# CHECK-NEXT: 10: nop
|
|
# CHECK-NEXT: 1f: nop
|
|
# CHECK-NEXT: 20: inc
|
|
|
|
# On Silvermont we emit only 7 byte NOPs since longer NOPs are not profitable
|
|
# SLM: 0: inc
|
|
# SLM-NEXT: 1: nop
|
|
# SLM-NEXT: 8: nop
|
|
# SLM-NEXT: f: nop
|
|
# SLM-NEXT: 16: nop
|
|
# SLM-NEXT: 1d: nop
|
|
# SLM-NEXT: 20: inc
|