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I've managed to convince myself that AArch64's acquire/release instructions are sufficient to guarantee C++11's required semantics, even in the sequentially-consistent case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179005 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
833 B
LLVM
27 lines
833 B
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
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define i32 @foo(i32* %var, i1 %cond) {
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; CHECK: foo:
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br i1 %cond, label %atomic_ver, label %simple_ver
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simple_ver:
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%oldval = load i32* %var
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%newval = add nsw i32 %oldval, -1
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store i32 %newval, i32* %var
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br label %somewhere
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atomic_ver:
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fence seq_cst
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%val = atomicrmw add i32* %var, i32 -1 monotonic
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fence seq_cst
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br label %somewhere
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; CHECK: dmb
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; CHECK: ldxr
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; CHECK: dmb
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; The key point here is that the second dmb isn't immediately followed by the
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; simple_ver basic block, which LLVM attempted to do when DMB had been marked
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; with isBarrier. For now, look for something that looks like "somewhere".
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; CHECK-NEXT: mov
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somewhere:
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%combined = phi i32 [ %val, %atomic_ver ], [ %newval, %simple_ver]
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ret i32 %combined
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}
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