Evan Cheng 2722e7b139 DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62519 91177308-0d34-0410-b5e6-96231b3b80d8		2009-01-19 19:06:11 +00:00
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Alpha	Fix Alpha test and support for private linkage.	2009-01-15 21:51:46 +00:00
ARM	Add the private linkage.	2009-01-15 20:18:42 +00:00
CBackend
CellSPU	Add the private linkage.	2009-01-15 20:18:42 +00:00
CPP
Generic	The list-td and list-tdrr schedulers don't yet support physreg	2009-01-13 20:24:13 +00:00
IA64	Add the private linkage.	2009-01-15 20:18:42 +00:00
Mips	Add the private linkage.	2009-01-15 20:18:42 +00:00
PowerPC	Fix PPC ISD::Declare isel and eliminate the need for PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's.	2009-01-16 22:57:32 +00:00
SPARC	Add the private linkage.	2009-01-15 20:18:42 +00:00
X86	DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it.	2009-01-19 19:06:11 +00:00
XCore	Add the private linkage.	2009-01-15 20:18:42 +00:00