mirror of
https://github.com/c64scene-ar/llvm-6502.git
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bab2adf496
and 64-bit code emitters that cannot share code unless we use virtual functions * Identify components being built by tablegen with more detail by assigning them to PowerPC, PPC32, or PPC64 more specifically; also avoids seeing 'building PowerPC XYZ' messages twice, where one is for PPC32 and one for PPC64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16980 91177308-0d34-0410-b5e6-96231b3b80d8
53 lines
2.1 KiB
Makefile
53 lines
2.1 KiB
Makefile
##===- lib/Target/PowerPC/Makefile -------------------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file was developed by the LLVM research group and is distributed under
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# the University of Illinois Open Source License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = powerpc
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include $(LEVEL)/Makefile.common
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TARGET = PowerPC
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
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PowerPCGenAsmWriter.inc PPC32GenCodeEmitter.inc \
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PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc \
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PPC64GenRegisterInfo.h.inc PPC64GenRegisterInfo.inc PPC64GenInstrInfo.inc
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TDFILES = $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td
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%GenRegisterNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET) register names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
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%GenRegisterInfo.h.inc:: %.td $(TDFILES) $(TBLGEN)
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@echo "Building `basename $<` register information header with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
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%GenRegisterInfo.inc:: %.td $(TDFILES) $(TBLGEN)
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@echo "Building `basename $<` register information implementation with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
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$(TARGET)GenInstrNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET) instruction names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
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%GenInstrInfo.inc:: %.td $(TDFILES) $(TBLGEN)
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@echo "Building `basename $<` instruction information with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
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%GenCodeEmitter.inc:: %.td $(TDFILES) $(TBLGEN)
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@echo "Building `basename $<` code emitter with tblgen"
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$(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
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$(TARGET)GenAsmWriter.inc:: $(TARGET).td $(TDFILES) $(TBLGEN)
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@echo "Building $(TARGET).td assembly writer with tblgen"
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$(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@
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clean::
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$(VERB) rm -f *.inc
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