mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8f2a85e099
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210903 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.6 KiB
LLVM
42 lines
1.6 KiB
LLVM
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@.str = private unnamed_addr constant [8 x i8] c"%d, %d\0A\00", align 1
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define i32 @foo(i32* %mem, i32 %val, i32 %c) nounwind {
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entry:
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%0 = atomicrmw add i32* %mem, i32 %val seq_cst
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%add = add nsw i32 %0, %c
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ret i32 %add
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; 16-LABEL: foo:
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; 16: lw ${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
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; 16: lw ${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
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}
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define i32 @main() nounwind {
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entry:
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%x = alloca i32, align 4
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store volatile i32 0, i32* %x, align 4
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%0 = atomicrmw add i32* %x, i32 1 seq_cst
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%add.i = add nsw i32 %0, 2
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%1 = load volatile i32* %x, align 4
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%call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %add.i, i32 %1) nounwind
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%pair = cmpxchg i32* %x, i32 1, i32 2 seq_cst seq_cst
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%2 = extractvalue { i32, i1 } %pair, 0
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%3 = load volatile i32* %x, align 4
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%call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %2, i32 %3) nounwind
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%4 = atomicrmw xchg i32* %x, i32 1 seq_cst
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%5 = load volatile i32* %x, align 4
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%call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %4, i32 %5) nounwind
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; 16-LABEL: main:
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; 16: lw ${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
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; 16: lw ${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
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; 16: lw ${{[0-9]+}}, %call16(__sync_val_compare_and_swap_4)(${{[0-9]+}})
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; 16: lw ${{[0-9]+}}, %call16(__sync_lock_test_and_set_4)(${{[0-9]+}})
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ret i32 0
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}
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declare i32 @printf(i8* nocapture, ...) nounwind
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