llvm-6502/test/CodeGen
Adam Nemet 293f71ddd2 [AVX512] Unpack support in new shuffle lowering
This now handles both 32 and 64-bit element sizes.

In this version, the test are in vector-shuffle-512-v8.ll, canonicalized by
Chandler's update_llc_test_checks.py.

Part of <rdar://problem/17688758>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225838 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-13 22:20:18 +00:00
..
AArch64 Fix PR22179. 2015-01-10 23:41:24 +00:00
ARM Debug info: Factor out the creation of DWARF expressions from AsmPrinter 2015-01-12 22:19:22 +00:00
CPP
Generic CodeGen: do not attempt to invalidate virtual registers for zero-sized phis. 2014-12-19 20:50:07 +00:00
Hexagon [Hexagon] Adding dealloc_return encoding and absolute address stores. 2015-01-06 16:15:15 +00:00
Inputs IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Mips [mips][microMIPS] Fix issue with 16b instructions in jr instruction delay slot 2015-01-13 15:59:17 +00:00
MSP430
NVPTX [NVPTX] Fix bugs related to isSingleValueType 2014-12-17 17:59:04 +00:00
PowerPC Use the integrated assembler as default on PowerPC 2015-01-13 19:43:45 +00:00
R600 R600: Implement getRsqrtEstimate 2015-01-13 20:53:18 +00:00
SPARC IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
SystemZ Use the integrated assembler as default on SystemZ 2015-01-13 19:45:16 +00:00
Thumb IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00
Thumb2 [ARM] Fix a bug in constant island pass that was triggering an assertion. 2015-01-08 20:44:50 +00:00
X86 [AVX512] Unpack support in new shuffle lowering 2015-01-13 22:20:18 +00:00
XCore IR: Make metadata typeless in assembly 2014-12-15 19:07:53 +00:00