Tanya Lattner 2a8eb722c7 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. ... Updated test case and reverted change to the PerfectShuffle Table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8		2011-05-18 06:42:21 +00:00
..
Alpha
ARM	In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32.	2011-05-18 06:42:21 +00:00
Blackfin
CBackend
CellSPU	don't test for codegen of 'store undef'	2011-04-09 02:31:26 +00:00
CPP
Generic	Move test for appropriate directory.	2011-05-17 19:06:43 +00:00
MBlaze	Add scheduling information for the MBlaze backend.	2011-04-11 22:31:52 +00:00
Mips	Remove LLVM IR metadata in test case committed in r130847.	2011-05-04 18:28:36 +00:00
MSP430	Fix register-dependent test in MSP430.	2011-05-04 01:01:39 +00:00
PowerPC	FileCheckize and break dependence on coalescing order.	2011-05-04 19:02:01 +00:00
PTX	PTX: add test cases for cvt, fneg, and selp	2011-05-10 14:53:13 +00:00
SPARC	Fix more register and coalescing dependencies.	2011-05-04 19:02:11 +00:00
SystemZ
Thumb	Move this test to CodeGen/Thumb. rdar://problem/9416774	2011-05-11 19:41:28 +00:00
Thumb2	Since I can't reproduce the failures from 131261, re-trying with a	2011-05-13 00:51:54 +00:00
X86	Make some of the fast-isel tests actually test fast-isel (and fix test failures).	2011-05-18 00:00:10 +00:00
XCore	Fix register-dependent XCore tests	2011-05-04 01:01:41 +00:00