llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-06 23:32:27 +00:00

History

Peter Collingbourne f86c29ea2c ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets.

This makes it more likely that we can use the 16-bit push and pop instructions
on Thumb-2, saving around 4 bytes per function.

Differential Revision: http://reviews.llvm.org/D9165

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235637 91177308-0d34-0410-b5e6-96231b3b80d8

2015-04-23 20:31:26 +00:00

AArch64

[AArch64] LORID_EL1 register must be treated as read-only

2015-04-20 16:54:37 +00:00

ARM

ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets.

2015-04-23 20:31:26 +00:00

AsmParser

Add support for .ifnes psuedo-op.

2015-03-18 14:20:54 +00:00

COFF

Add a proper fix for pr23025.