Jim Grosbach 2c6363a62d ARM assembly parsing and encoding for RFE instruction. ... Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-29 18:47:24 +00:00
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CodeGen	Fix two tests that I crashed in the previous commits. The mask elts	2011-07-29 02:05:28 +00:00
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Feature	Merge the contents from exception-handling-rewrite to the mainline.	2011-07-27 20:18:04 +00:00
FrontendC++	Due to changes coming from the new LLVM type system, you now get	2011-07-28 12:21:47 +00:00
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MC	ARM assembly parsing and encoding for RFE instruction.	2011-07-29 18:47:24 +00:00
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Transforms	Make sure to correctly clear the exact/nuw/nsw flags off of shifts when they are combined together. <rdar://problem/9859829>	2011-07-29 00:18:19 +00:00
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