Jim Grosbach 2c6363a62d ARM assembly parsing and encoding for RFE instruction. ... Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8		2011-07-29 18:47:24 +00:00
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ARM	ARM assembly parsing and encoding for RFE instruction.	2011-07-29 18:47:24 +00:00
AsmParser	Move some ELF directives into ELF asm parser.	2011-07-25 17:55:35 +00:00
COFF	Add the suffix to the Win64 EH data sections' names if given. Add a test for	2011-05-27 21:38:47 +00:00
Disassembler	Tweak ARM assembly parsing and printing of MSR instruction.	2011-07-19 22:45:10 +00:00
ELF	Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.	2011-07-20 19:36:11 +00:00
MachO	Move ARM-specific test to ARM directory.	2011-06-25 01:53:17 +00:00
MBlaze	Teach the MBlaze asm parser how to parse special purpose register names.	2010-12-20 20:43:24 +00:00
X86	Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.	2011-07-27 23:22:03 +00:00