llvm-6502/test/CodeGen/X86
Evan Cheng e41ebccafd Update test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28216 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-10 19:53:05 +00:00
..
.cvsignore Tired of wading through cvs's list ? files that are generated when building 2006-03-23 23:41:57 +00:00
2002-12-23-LocalRAProblem.llx
2002-12-23-SubProblem.llx
2003-08-03-CallArgLiveRanges.llx
2003-08-23-DeadBlockTest.llx
2003-11-03-GlobalBool.llx
2004-02-12-Memcpy.llx
2004-02-13-FrameReturnAddress.llx
2004-02-14-InefficientStackPointer.llx
2004-02-22-Casts.llx
2004-03-30-Select-Max.llx
2004-04-09-SameValueCoalescing.llx
2004-04-13-FPCMOV-Crash.llx
2004-06-10-StackifierCrash.llx
2004-10-08-SelectSetCCFold.llx
2005-01-17-CycleInDAG.ll
2005-02-14-IllegalAssembler.ll
2005-05-08-FPStackifierPHI.ll
2005-08-30-RegAllocAliasProblem.ll Intel mode no longer uses %'s on registers 2006-05-01 05:56:51 +00:00
2005-12-03-IndirectTailCall.ll Intel mode no longer uses %'s on registers 2006-05-01 05:56:51 +00:00
2006-01-19-ISelFoldingBug.ll
2006-01-30-LongSetcc.ll
2006-03-01-InstrSchedBug.ll
2006-03-02-InstrSchedBug.ll
2006-04-04-CrossBlockCrash.ll new testcase 2006-04-05 06:54:14 +00:00
2006-04-27-ISelFoldingBug.ll Test case for PR748 2006-04-28 01:21:37 +00:00
2006-05-01-SchedCausingSpills.ll A few instruction scheduling test cases. 2006-05-03 02:11:36 +00:00
2006-05-02-InstrSched1.ll A few instruction scheduling test cases. 2006-05-03 02:11:36 +00:00
2006-05-02-InstrSched2.ll A few instruction scheduling test cases. 2006-05-03 02:11:36 +00:00
2006-05-08-CoalesceSubRegClass.ll Test case for PR770 2006-05-09 06:48:12 +00:00
2006-05-08-InstrSched.ll Update test case 2006-05-10 19:53:05 +00:00
bswap.ll
commute-two-addr.ll
compare_folding.llx
compare-add.ll
dg.exp Added the ability to xfail based on llvmgcc version 2006-04-12 21:57:40 +00:00
extend.ll
fabs.ll Also requires -mattr=-sse3 2006-03-15 18:05:13 +00:00
fast-cc-callee-pops.ll update testcases for x86 fastcc changes. 2006-03-18 23:48:54 +00:00
fast-cc-merge-stack-adj.ll Intel mode no longer uses %'s on registers 2006-05-01 05:56:51 +00:00
fast-cc-pass-in-regs.ll Intel mode no longer uses %'s on registers 2006-05-01 05:56:51 +00:00
fast-cc-tail-call.ll
fildll.ll
fp_constant_op.llx
fp_load_cast_fold.llx
fp_load_fold.llx
fp-immediate-shorten.ll Also requires -mattr=-sse3 2006-03-15 18:05:13 +00:00
imul-lea.ll
isnan.llx
lea.ll
loop-strength-reduce.ll Option -enable-x86-lsr has been removed 2006-03-20 18:26:11 +00:00
mul-shift-reassoc.ll
negatize_zero.ll Also requires -mattr=-sse3 2006-03-15 18:05:13 +00:00
overlap-add.ll Intel mode no longer uses %'s on registers 2006-05-01 05:56:51 +00:00
overlap-shift.ll Intel mode no longer uses %'s on registers 2006-05-01 05:56:51 +00:00
rdtsc.ll
regpressure.ll
rotate.ll
select.ll
setuge.ll
shift-double.llx
shift-folding.ll
shift-one.ll
sse-load-ret.ll
store_op_load_fold2.ll Add a test case for (store (op (load ..) ..) ..) folding. 2006-03-09 19:04:30 +00:00
store_op_load_fold.ll weak globals on darwin require an extra load, breaking this test 2006-03-10 17:55:10 +00:00
store-fp-constant.ll
store-global-address.ll
unpcklps.ll new testcase 2006-03-28 20:32:12 +00:00
vec_clear.ll Check for llc crash. 2006-04-21 01:21:23 +00:00
vec_extract.ll Add && to each RUN: line (except the last one). 2006-04-21 04:58:23 +00:00
vec_insert.ll Add && to each RUN: line (except the last one). 2006-04-21 04:58:23 +00:00
vec_return.ll New testcase 2006-04-17 20:32:27 +00:00
vec_select.ll Add a vselect test case. 2006-04-10 07:30:13 +00:00
vec_set-2.ll Add && to each RUN: line (except the last one). 2006-04-21 04:58:23 +00:00
vec_set-3.ll Add && to each RUN: line (except the last one). 2006-04-21 04:58:23 +00:00
vec_set-4.ll Add && to each RUN: line (except the last one). 2006-04-21 04:58:23 +00:00
vec_set-5.ll Two more build_vector tests. 2006-04-22 06:19:11 +00:00
vec_set-6.ll Two more build_vector tests. 2006-04-22 06:19:11 +00:00
vec_set-7.ll Added a movq test case. 2006-04-24 23:03:22 +00:00
vec_set.ll Add a BUILD_VECTOR with unpack and interleave testcase. 2006-03-25 09:48:14 +00:00
vec_shuffle-2.ll Add && to each RUN: line (except the last one). 2006-04-21 04:58:23 +00:00
vec_shuffle-3.ll Add && to each RUN: line (except the last one). 2006-04-21 04:58:23 +00:00
vec_shuffle-4.ll Update. It should use two shufps, not three! 2006-04-28 18:55:34 +00:00
vec_shuffle-5.ll Use movsd to shuffle in the lowest two elements of a v4f32 / v4i32 vector when 2006-05-03 20:32:03 +00:00
vec_shuffle.ll Add && to each RUN: line (except the last one). 2006-04-21 04:58:23 +00:00
vec_splat-2.ll v16i8 splat with 2 punpcklbw and a single pshufd. 2006-04-20 09:05:16 +00:00
vec_splat.ll movddup is a SSE3 instruction. 2006-04-21 16:42:47 +00:00
vec_zero.ll Add && to each RUN: line (except the last one). 2006-04-21 04:58:23 +00:00