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basic-block segments bottom-up instead of top down. This is the first step in a general restructuring of the way register liveness is tracked in the post-RA scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63643 91177308-0d34-0410-b5e6-96231b3b80d8
813 lines
30 KiB
C++
813 lines
30 KiB
C++
//===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a top-down list scheduler, using standard algorithms.
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// The basic approach uses a priority queue of available nodes to schedule.
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// One at a time, nodes are taken from the priority queue (thus in priority
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// order), checked for legality to schedule, and emitted if legal.
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//
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// Nodes may not be legal to schedule either due to structural hazards (e.g.
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// pipeline or resource constraints) or because an input to the instruction has
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// not completed execution.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "post-RA-sched"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/LatencyPriorityQueue.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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#include <map>
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using namespace llvm;
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STATISTIC(NumNoops, "Number of noops inserted");
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STATISTIC(NumStalls, "Number of pipeline stalls");
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static cl::opt<bool>
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EnableAntiDepBreaking("break-anti-dependencies",
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cl::desc("Break post-RA scheduling anti-dependencies"),
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cl::init(true), cl::Hidden);
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static cl::opt<bool>
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EnablePostRAHazardAvoidance("avoid-hazards",
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cl::desc("Enable simple hazard-avoidance"),
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cl::init(true), cl::Hidden);
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namespace {
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class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
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public:
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static char ID;
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PostRAScheduler() : MachineFunctionPass(&ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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const char *getPassName() const {
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return "Post RA top-down list latency scheduler";
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}
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bool runOnMachineFunction(MachineFunction &Fn);
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};
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char PostRAScheduler::ID = 0;
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class VISIBILITY_HIDDEN SchedulePostRATDList : public ScheduleDAGInstrs {
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/// AvailableQueue - The priority queue to use for the available SUnits.
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///
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LatencyPriorityQueue AvailableQueue;
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/// PendingQueue - This contains all of the instructions whose operands have
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/// been issued, but their results are not ready yet (due to the latency of
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/// the operation). Once the operands becomes available, the instruction is
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/// added to the AvailableQueue.
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std::vector<SUnit*> PendingQueue;
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/// Topo - A topological ordering for SUnits.
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ScheduleDAGTopologicalSort Topo;
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/// AllocatableSet - The set of allocatable registers.
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/// We'll be ignoring anti-dependencies on non-allocatable registers,
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/// because they may not be safe to break.
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const BitVector AllocatableSet;
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/// HazardRec - The hazard recognizer to use.
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ScheduleHazardRecognizer *HazardRec;
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public:
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SchedulePostRATDList(MachineFunction &MF,
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const MachineLoopInfo &MLI,
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const MachineDominatorTree &MDT,
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ScheduleHazardRecognizer *HR)
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: ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
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AllocatableSet(TRI->getAllocatableSet(MF)),
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HazardRec(HR) {}
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~SchedulePostRATDList() {
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delete HazardRec;
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}
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void Schedule();
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private:
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void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
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void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
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void ListScheduleTopDown();
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bool BreakAntiDependencies();
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};
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/// SimpleHazardRecognizer - A *very* simple hazard recognizer. It uses
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/// a coarse classification and attempts to avoid that instructions of
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/// a given class aren't grouped too densely together.
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class SimpleHazardRecognizer : public ScheduleHazardRecognizer {
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/// Class - A simple classification for SUnits.
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enum Class {
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Other, Load, Store
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};
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/// Window - The Class values of the most recently issued
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/// instructions.
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Class Window[8];
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/// getClass - Classify the given SUnit.
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Class getClass(const SUnit *SU) {
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const MachineInstr *MI = SU->getInstr();
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const TargetInstrDesc &TID = MI->getDesc();
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if (TID.mayLoad())
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return Load;
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if (TID.mayStore())
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return Store;
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return Other;
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}
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/// Step - Rotate the existing entries in Window and insert the
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/// given class value in position as the most recent.
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void Step(Class C) {
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std::copy(Window+1, array_endof(Window), Window);
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Window[array_lengthof(Window)-1] = C;
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}
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public:
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SimpleHazardRecognizer() : Window() {}
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virtual HazardType getHazardType(SUnit *SU) {
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Class C = getClass(SU);
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if (C == Other)
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return NoHazard;
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unsigned Score = 0;
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for (unsigned i = 0; i != array_lengthof(Window); ++i)
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if (Window[i] == C)
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Score += i + 1;
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if (Score > array_lengthof(Window) * 2)
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return Hazard;
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return NoHazard;
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}
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virtual void EmitInstruction(SUnit *SU) {
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Step(getClass(SU));
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}
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virtual void AdvanceCycle() {
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Step(Other);
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}
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};
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}
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bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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DOUT << "PostRAScheduler\n";
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const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
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const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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ScheduleHazardRecognizer *HR = EnablePostRAHazardAvoidance ?
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new SimpleHazardRecognizer :
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new ScheduleHazardRecognizer();
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SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR);
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// Loop over all of the basic blocks
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB) {
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// Schedule each sequence of instructions not interrupted by a label
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// or anything else that effectively needs to shut down scheduling.
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MachineBasicBlock::iterator Current = MBB->end(), Top = MBB->begin();
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for (MachineBasicBlock::iterator I = Current; I != Top; ) {
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MachineInstr *MI = --I;
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if (MI->getDesc().isTerminator() || MI->isLabel()) {
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Scheduler.Run(0, MBB, next(I), Current);
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Scheduler.EmitSchedule();
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Current = I;
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}
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}
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Scheduler.Run(0, MBB, Top, Current);
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Scheduler.EmitSchedule();
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}
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return true;
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}
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/// Schedule - Schedule the DAG using list scheduling.
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void SchedulePostRATDList::Schedule() {
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DOUT << "********** List Scheduling **********\n";
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// Build the scheduling graph.
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BuildSchedGraph();
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if (EnableAntiDepBreaking) {
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if (BreakAntiDependencies()) {
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// We made changes. Update the dependency graph.
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// Theoretically we could update the graph in place:
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// When a live range is changed to use a different register, remove
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// the def's anti-dependence *and* output-dependence edges due to
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// that register, and add new anti-dependence and output-dependence
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// edges based on the next live range of the register.
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SUnits.clear();
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BuildSchedGraph();
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}
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}
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AvailableQueue.initNodes(SUnits);
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ListScheduleTopDown();
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AvailableQueue.releaseState();
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}
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/// getInstrOperandRegClass - Return register class of the operand of an
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/// instruction of the specified TargetInstrDesc.
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static const TargetRegisterClass*
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getInstrOperandRegClass(const TargetRegisterInfo *TRI,
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const TargetInstrInfo *TII, const TargetInstrDesc &II,
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unsigned Op) {
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if (Op >= II.getNumOperands())
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return NULL;
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if (II.OpInfo[Op].isLookupPtrRegClass())
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return TII->getPointerRegClass();
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return TRI->getRegClass(II.OpInfo[Op].RegClass);
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}
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/// CriticalPathStep - Return the next SUnit after SU on the bottom-up
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/// critical path.
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static SDep *CriticalPathStep(SUnit *SU) {
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SDep *Next = 0;
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unsigned NextDepth = 0;
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// Find the predecessor edge with the greatest depth.
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for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
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P != PE; ++P) {
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SUnit *PredSU = P->getSUnit();
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unsigned PredLatency = P->getLatency();
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unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
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// In the case of a latency tie, prefer an anti-dependency edge over
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// other types of edges.
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if (NextDepth < PredTotalLatency ||
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(NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
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NextDepth = PredTotalLatency;
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Next = &*P;
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}
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}
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return Next;
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}
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/// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
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/// of the ScheduleDAG and break them by renaming registers.
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///
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bool SchedulePostRATDList::BreakAntiDependencies() {
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// The code below assumes that there is at least one instruction,
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// so just duck out immediately if the block is empty.
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if (SUnits.empty()) return false;
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// Find the node at the bottom of the critical path.
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SUnit *Max = 0;
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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SUnit *SU = &SUnits[i];
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if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
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Max = SU;
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}
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DOUT << "Critical path has total latency "
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<< (Max->getDepth() + Max->Latency) << "\n";
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// Track progress along the critical path through the SUnit graph as we walk
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// the instructions.
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SUnit *CriticalPathSU = Max;
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MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
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// For live regs that are only used in one register class in a live range,
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// the register class. If the register is not live, the corresponding value
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// is null. If the register is live but used in multiple register classes,
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// the corresponding value is -1 casted to a pointer.
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const TargetRegisterClass *
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Classes[TargetRegisterInfo::FirstVirtualRegister] = {};
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// Map registers to all their references within a live range.
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std::multimap<unsigned, MachineOperand *> RegRefs;
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// The index of the most recent kill (proceding bottom-up), or ~0u if
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// the register is not live.
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unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
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std::fill(KillIndices, array_endof(KillIndices), ~0u);
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// The index of the most recent complete def (proceding bottom up), or ~0u if
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// the register is live.
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unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
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std::fill(DefIndices, array_endof(DefIndices), BB->size());
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// Determine the live-out physregs for this block.
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if (BB->back().getDesc().isReturn())
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// In a return block, examine the function live-out regs.
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for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
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E = MRI.liveout_end(); I != E; ++I) {
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unsigned Reg = *I;
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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}
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}
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else
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// In a non-return block, examine the live-in regs of all successors.
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for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
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SE = BB->succ_end(); SI != SE; ++SI)
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for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
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E = (*SI)->livein_end(); I != E; ++I) {
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unsigned Reg = *I;
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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}
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}
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// Consider callee-saved registers as live-out, since we're running after
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// prologue/epilogue insertion so there's no way to add additional
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// saved registers.
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//
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// TODO: If the callee saves and restores these, then we can potentially
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// use them between the save and the restore. To do that, we could scan
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// the exit blocks to see which of these registers are defined.
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// Alternatively, callee-saved registers that aren't saved and restored
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// could be marked live-in in every block.
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for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
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unsigned Reg = *I;
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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}
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}
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// Consider this pattern:
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// A = ...
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// ... = A
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// A = ...
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// ... = A
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// A = ...
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// ... = A
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// A = ...
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// ... = A
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// There are three anti-dependencies here, and without special care,
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// we'd break all of them using the same register:
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// A = ...
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// ... = A
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// B = ...
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// ... = B
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// B = ...
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// ... = B
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// B = ...
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// ... = B
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// because at each anti-dependence, B is the first register that
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// isn't A which is free. This re-introduces anti-dependencies
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// at all but one of the original anti-dependencies that we were
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// trying to break. To avoid this, keep track of the most recent
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// register that each register was replaced with, avoid avoid
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// using it to repair an anti-dependence on the same register.
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// This lets us produce this:
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// A = ...
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// ... = A
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// B = ...
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// ... = B
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// C = ...
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// ... = C
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// B = ...
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// ... = B
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// This still has an anti-dependence on B, but at least it isn't on the
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// original critical path.
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//
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// TODO: If we tracked more than one register here, we could potentially
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// fix that remaining critical edge too. This is a little more involved,
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// because unlike the most recent register, less recent registers should
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// still be considered, though only if no other registers are available.
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unsigned LastNewReg[TargetRegisterInfo::FirstVirtualRegister] = {};
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// Attempt to break anti-dependence edges on the critical path. Walk the
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// instructions from the bottom up, tracking information about liveness
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// as we go to help determine which registers are available.
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bool Changed = false;
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unsigned Count = SUnits.size() - 1;
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for (MachineBasicBlock::iterator I = End, E = Begin;
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I != E; --Count) {
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MachineInstr *MI = --I;
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// After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
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// dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
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// is left behind appearing to clobber the super-register, while the
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// subregister needs to remain live. So we just ignore them.
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if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
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continue;
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// Check if this instruction has a dependence on the critical path that
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// is an anti-dependence that we may be able to break. If it is, set
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// AntiDepReg to the non-zero register associated with the anti-dependence.
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//
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// We limit our attention to the critical path as a heuristic to avoid
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// breaking anti-dependence edges that aren't going to significantly
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// impact the overall schedule. There are a limited number of registers
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// and we want to save them for the important edges.
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//
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// TODO: Instructions with multiple defs could have multiple
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// anti-dependencies. The current code here only knows how to break one
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// edge per instruction. Note that we'd have to be able to break all of
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// the anti-dependencies in an instruction in order to be effective.
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unsigned AntiDepReg = 0;
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if (MI == CriticalPathMI) {
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if (SDep *Edge = CriticalPathStep(CriticalPathSU)) {
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SUnit *NextSU = Edge->getSUnit();
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// Only consider anti-dependence edges.
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if (Edge->getKind() == SDep::Anti) {
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AntiDepReg = Edge->getReg();
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assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
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// Don't break anti-dependencies on non-allocatable registers.
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if (!AllocatableSet.test(AntiDepReg))
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AntiDepReg = 0;
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else {
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// If the SUnit has other dependencies on the SUnit that it
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// anti-depends on, don't bother breaking the anti-dependency
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// since those edges would prevent such units from being
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// scheduled past each other regardless.
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//
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// Also, if there are dependencies on other SUnits with the
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// same register as the anti-dependency, don't attempt to
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// break it.
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for (SUnit::pred_iterator P = CriticalPathSU->Preds.begin(),
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PE = CriticalPathSU->Preds.end(); P != PE; ++P)
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if (P->getSUnit() == NextSU ?
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(P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
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(P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
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AntiDepReg = 0;
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break;
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}
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}
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}
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CriticalPathSU = NextSU;
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CriticalPathMI = CriticalPathSU->getInstr();
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} else {
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// We've reached the end of the critical path.
|
|
CriticalPathSU = 0;
|
|
CriticalPathMI = 0;
|
|
}
|
|
}
|
|
|
|
// Scan the register operands for this instruction and update
|
|
// Classes and RegRefs.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
const TargetRegisterClass *NewRC =
|
|
getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
|
|
|
|
// If this instruction has a use of AntiDepReg, breaking it
|
|
// is invalid.
|
|
if (MO.isUse() && AntiDepReg == Reg)
|
|
AntiDepReg = 0;
|
|
|
|
// For now, only allow the register to be changed if its register
|
|
// class is consistent across all uses.
|
|
if (!Classes[Reg] && NewRC)
|
|
Classes[Reg] = NewRC;
|
|
else if (!NewRC || Classes[Reg] != NewRC)
|
|
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
|
|
|
// Now check for aliases.
|
|
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
|
|
// If an alias of the reg is used during the live range, give up.
|
|
// Note that this allows us to skip checking if AntiDepReg
|
|
// overlaps with any of the aliases, among other things.
|
|
unsigned AliasReg = *Alias;
|
|
if (Classes[AliasReg]) {
|
|
Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
|
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
|
}
|
|
}
|
|
|
|
// If we're still willing to consider this register, note the reference.
|
|
if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
|
|
RegRefs.insert(std::make_pair(Reg, &MO));
|
|
}
|
|
|
|
// Determine AntiDepReg's register class, if it is live and is
|
|
// consistently used within a single class.
|
|
const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
|
|
assert((AntiDepReg == 0 || RC != NULL) &&
|
|
"Register should be live if it's causing an anti-dependence!");
|
|
if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
|
|
AntiDepReg = 0;
|
|
|
|
// Look for a suitable register to use to break the anti-depenence.
|
|
//
|
|
// TODO: Instead of picking the first free register, consider which might
|
|
// be the best.
|
|
if (AntiDepReg != 0) {
|
|
for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF),
|
|
RE = RC->allocation_order_end(MF); R != RE; ++R) {
|
|
unsigned NewReg = *R;
|
|
// Don't replace a register with itself.
|
|
if (NewReg == AntiDepReg) continue;
|
|
// Don't replace a register with one that was recently used to repair
|
|
// an anti-dependence with this AntiDepReg, because that would
|
|
// re-introduce that anti-dependence.
|
|
if (NewReg == LastNewReg[AntiDepReg]) continue;
|
|
// If NewReg is dead and NewReg's most recent def is not before
|
|
// AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
|
|
assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) &&
|
|
"Kill and Def maps aren't consistent for AntiDepReg!");
|
|
assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) &&
|
|
"Kill and Def maps aren't consistent for NewReg!");
|
|
if (KillIndices[NewReg] == ~0u &&
|
|
Classes[NewReg] != reinterpret_cast<TargetRegisterClass *>(-1) &&
|
|
KillIndices[AntiDepReg] <= DefIndices[NewReg]) {
|
|
DOUT << "Breaking anti-dependence edge on "
|
|
<< TRI->getName(AntiDepReg)
|
|
<< " with " << RegRefs.count(AntiDepReg) << " references"
|
|
<< " using " << TRI->getName(NewReg) << "!\n";
|
|
|
|
// Update the references to the old register to refer to the new
|
|
// register.
|
|
std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
|
|
std::multimap<unsigned, MachineOperand *>::iterator>
|
|
Range = RegRefs.equal_range(AntiDepReg);
|
|
for (std::multimap<unsigned, MachineOperand *>::iterator
|
|
Q = Range.first, QE = Range.second; Q != QE; ++Q)
|
|
Q->second->setReg(NewReg);
|
|
|
|
// We just went back in time and modified history; the
|
|
// liveness information for the anti-depenence reg is now
|
|
// inconsistent. Set the state as if it were dead.
|
|
Classes[NewReg] = Classes[AntiDepReg];
|
|
DefIndices[NewReg] = DefIndices[AntiDepReg];
|
|
KillIndices[NewReg] = KillIndices[AntiDepReg];
|
|
|
|
Classes[AntiDepReg] = 0;
|
|
DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
|
|
KillIndices[AntiDepReg] = ~0u;
|
|
|
|
RegRefs.erase(AntiDepReg);
|
|
Changed = true;
|
|
LastNewReg[AntiDepReg] = NewReg;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Update liveness.
|
|
// Proceding upwards, registers that are defed but not used in this
|
|
// instruction are now dead.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
if (!MO.isDef()) continue;
|
|
// Ignore two-addr defs.
|
|
if (MI->isRegReDefinedByTwoAddr(i)) continue;
|
|
|
|
DefIndices[Reg] = Count;
|
|
KillIndices[Reg] = ~0u;
|
|
Classes[Reg] = 0;
|
|
RegRefs.erase(Reg);
|
|
// Repeat, for all subregs.
|
|
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
|
|
*Subreg; ++Subreg) {
|
|
unsigned SubregReg = *Subreg;
|
|
DefIndices[SubregReg] = Count;
|
|
KillIndices[SubregReg] = ~0u;
|
|
Classes[SubregReg] = 0;
|
|
RegRefs.erase(SubregReg);
|
|
}
|
|
// Conservatively mark super-registers as unusable.
|
|
for (const unsigned *Super = TRI->getSuperRegisters(Reg);
|
|
*Super; ++Super) {
|
|
unsigned SuperReg = *Super;
|
|
Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
|
}
|
|
}
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg()) continue;
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg == 0) continue;
|
|
if (!MO.isUse()) continue;
|
|
|
|
const TargetRegisterClass *NewRC =
|
|
getInstrOperandRegClass(TRI, TII, MI->getDesc(), i);
|
|
|
|
// For now, only allow the register to be changed if its register
|
|
// class is consistent across all uses.
|
|
if (!Classes[Reg] && NewRC)
|
|
Classes[Reg] = NewRC;
|
|
else if (!NewRC || Classes[Reg] != NewRC)
|
|
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
|
|
|
RegRefs.insert(std::make_pair(Reg, &MO));
|
|
|
|
// It wasn't previously live but now it is, this is a kill.
|
|
if (KillIndices[Reg] == ~0u) {
|
|
KillIndices[Reg] = Count;
|
|
DefIndices[Reg] = ~0u;
|
|
}
|
|
// Repeat, for all aliases.
|
|
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
|
|
unsigned AliasReg = *Alias;
|
|
if (KillIndices[AliasReg] == ~0u) {
|
|
KillIndices[AliasReg] = Count;
|
|
DefIndices[AliasReg] = ~0u;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
assert(Count == ~0u && "Count mismatch!");
|
|
|
|
return Changed;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Top-Down Scheduling
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
|
|
/// the PendingQueue if the count reaches zero. Also update its cycle bound.
|
|
void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
|
|
SUnit *SuccSU = SuccEdge->getSUnit();
|
|
--SuccSU->NumPredsLeft;
|
|
|
|
#ifndef NDEBUG
|
|
if (SuccSU->NumPredsLeft < 0) {
|
|
cerr << "*** Scheduling failed! ***\n";
|
|
SuccSU->dump(this);
|
|
cerr << " has been released too many times!\n";
|
|
assert(0);
|
|
}
|
|
#endif
|
|
|
|
// Compute how many cycles it will be before this actually becomes
|
|
// available. This is the max of the start time of all predecessors plus
|
|
// their latencies.
|
|
SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
|
|
|
|
if (SuccSU->NumPredsLeft == 0) {
|
|
PendingQueue.push_back(SuccSU);
|
|
}
|
|
}
|
|
|
|
/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
|
|
/// count of its successors. If a successor pending count is zero, add it to
|
|
/// the Available queue.
|
|
void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
|
|
DOUT << "*** Scheduling [" << CurCycle << "]: ";
|
|
DEBUG(SU->dump(this));
|
|
|
|
Sequence.push_back(SU);
|
|
assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
|
|
SU->setDepthToAtLeast(CurCycle);
|
|
|
|
// Top down: release successors.
|
|
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I)
|
|
ReleaseSucc(SU, &*I);
|
|
|
|
SU->isScheduled = true;
|
|
AvailableQueue.ScheduledNode(SU);
|
|
}
|
|
|
|
/// ListScheduleTopDown - The main loop of list scheduling for top-down
|
|
/// schedulers.
|
|
void SchedulePostRATDList::ListScheduleTopDown() {
|
|
unsigned CurCycle = 0;
|
|
|
|
// All leaves to Available queue.
|
|
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
|
// It is available if it has no predecessors.
|
|
if (SUnits[i].Preds.empty()) {
|
|
AvailableQueue.push(&SUnits[i]);
|
|
SUnits[i].isAvailable = true;
|
|
}
|
|
}
|
|
|
|
// While Available queue is not empty, grab the node with the highest
|
|
// priority. If it is not ready put it back. Schedule the node.
|
|
std::vector<SUnit*> NotReady;
|
|
Sequence.reserve(SUnits.size());
|
|
while (!AvailableQueue.empty() || !PendingQueue.empty()) {
|
|
// Check to see if any of the pending instructions are ready to issue. If
|
|
// so, add them to the available queue.
|
|
unsigned MinDepth = ~0u;
|
|
for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
|
|
if (PendingQueue[i]->getDepth() <= CurCycle) {
|
|
AvailableQueue.push(PendingQueue[i]);
|
|
PendingQueue[i]->isAvailable = true;
|
|
PendingQueue[i] = PendingQueue.back();
|
|
PendingQueue.pop_back();
|
|
--i; --e;
|
|
} else if (PendingQueue[i]->getDepth() < MinDepth)
|
|
MinDepth = PendingQueue[i]->getDepth();
|
|
}
|
|
|
|
// If there are no instructions available, don't try to issue anything, and
|
|
// don't advance the hazard recognizer.
|
|
if (AvailableQueue.empty()) {
|
|
CurCycle = MinDepth != ~0u ? MinDepth : CurCycle + 1;
|
|
continue;
|
|
}
|
|
|
|
SUnit *FoundSUnit = 0;
|
|
|
|
bool HasNoopHazards = false;
|
|
while (!AvailableQueue.empty()) {
|
|
SUnit *CurSUnit = AvailableQueue.pop();
|
|
|
|
ScheduleHazardRecognizer::HazardType HT =
|
|
HazardRec->getHazardType(CurSUnit);
|
|
if (HT == ScheduleHazardRecognizer::NoHazard) {
|
|
FoundSUnit = CurSUnit;
|
|
break;
|
|
}
|
|
|
|
// Remember if this is a noop hazard.
|
|
HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
|
|
|
|
NotReady.push_back(CurSUnit);
|
|
}
|
|
|
|
// Add the nodes that aren't ready back onto the available list.
|
|
if (!NotReady.empty()) {
|
|
AvailableQueue.push_all(NotReady);
|
|
NotReady.clear();
|
|
}
|
|
|
|
// If we found a node to schedule, do it now.
|
|
if (FoundSUnit) {
|
|
ScheduleNodeTopDown(FoundSUnit, CurCycle);
|
|
HazardRec->EmitInstruction(FoundSUnit);
|
|
|
|
// If this is a pseudo-op node, we don't want to increment the current
|
|
// cycle.
|
|
if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops!
|
|
++CurCycle;
|
|
} else if (!HasNoopHazards) {
|
|
// Otherwise, we have a pipeline stall, but no other problem, just advance
|
|
// the current cycle and try again.
|
|
DOUT << "*** Advancing cycle, no work to do\n";
|
|
HazardRec->AdvanceCycle();
|
|
++NumStalls;
|
|
++CurCycle;
|
|
} else {
|
|
// Otherwise, we have no instructions to issue and we have instructions
|
|
// that will fault if we don't do this right. This is the case for
|
|
// processors without pipeline interlocks and other cases.
|
|
DOUT << "*** Emitting noop\n";
|
|
HazardRec->EmitNoop();
|
|
Sequence.push_back(0); // NULL here means noop
|
|
++NumNoops;
|
|
++CurCycle;
|
|
}
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
VerifySchedule(/*isBottomUp=*/false);
|
|
#endif
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Public Constructor Functions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
FunctionPass *llvm::createPostRAScheduler() {
|
|
return new PostRAScheduler();
|
|
}
|